ADP3025 데이터 시트보기 (PDF) - Analog Devices
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ADP3025 Datasheet PDF : 24 Pages
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ADP3025
COMPENSATION LOOP DESIGN AND TEST
METHOD
1. Choose the gain (R2/R1) for the desired bandwidth.
2. Place fZ1 20% to 30% below fLC.
2. Whenever high currents must be routed between PCB
layers, vias should be used liberally to create several parallel
current paths so that the resistance and inductance
introduced by these current paths is minimized and the via
current rating is not exceeded.
3. Place fZ2 20% to 30% above fLC.
3. The power and ground planes should overlap each other as
4. Place fP1 at fESR. Check the output capacitor for worst-case
ESR tolerances.
little as possible. It is generally easiest (although not
necessary) to have the power and signal ground planes on
the same PCB layer. The planes should be connected
5. Place fP2 at 40% to 60% of the oscillator frequency.
nearest to the first input capacitor where the input ground
current flows from the converter back to the battery.
6. Estimate phase margins in full frequency range (zero
frequency to zero gain crossing frequency).
7. Apply the designed compensation and test the transient
response under a moderate step load change (30% to 60%)
E and various input voltages. Monitor the output voltage via
an oscilloscope. The voltage overshoot or undershoot
should be within 1% to 3% of the nominal output, without
T ringing and abnormal oscillation.
RECOMMENDED APPLICATIONS
1. ADP3025’s switching channels are recommended to
E generate output current no greater than 5 A each. The
maximum current output capability is subject to the
limitation of ADP3025’s gate driving capability and its
L maximum voltage rating.
2. For a system with input voltage up to 20 V, the ADP3025
can be used to generate 5 V/3.3 V system power rails at
O 200 kHz. Switching frequency of 300 kHz is not recom-
mended because the worst-case on time of the top
MOSFET is too narrow (~500 ns), leaving no room for
current sensing.
S 3. For applications that use the silver box’s 12 V rail as the
input source, the ADP3025 can be configured to generate
5 V/3.3 V rails at both 200 kHz and 300 kHz.
B LAYOUT CONSIDERATIONS
The following guidelines are recommended for optimal
O performance of a switching regulator in a portable PC system:
4. If critical signal lines (including the voltage and current
sense lines of the ADP3025) must cross through power
circuitry, it is best if a signal ground plane can be inter-
posed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of making signal
ground a bit noisier.
5. The PGND1and PGND2 pins of the ADP3025 should
connect first to a ceramic bypass capacitor on the VIN pin
and then to the power ground plane, using the shortest
possible trace. However, the power ground plane should
not extend under other signal components, including the
ADP3025 itself. If necessary, follow the preceding guideline
to use the signal plane as a shield between the power
ground plane and the signal circuitry.
6. The AGND pin of the ADP3025 should connect first to the
REF capacitor, and then to the signal ground plane. In cases
where no signal ground plane can be used, short intercon-
nections to other signal ground circuitry in the power
converter should be used.
7. The output capacitors of the power converter should be
connected to the signal ground plane even though power
current flows in the ground of these capacitors. For this
reason, it is advisable to avoid critical ground connections
(e.g., the signal circuitry of the power converter) in the
signal ground plane between the input and output capaci-
tors. It is also advisable to keep the planar interconnection
path short (i.e., have input and output capacitors close
General Recommendations
together).
1. For best results, a (minimum) 4-layer PCB is recommen-
ded. This should allow the needed versatility for control
circuitry interconnections with optimal placement, a signal
ground plane, power planes for both power ground and the
input power, and wide interconnection traces in the rest of
the power delivery current paths. Each square unit of 1 oz.
8. The output capacitors should also be connected as close as
possible to the load (or connector) that receives the power.
If the load is distributed, the capacitors should also be
distributed, generally in proportion to where the load tends
to be more dynamic.
copper trace has a resistance of ~0.53 mΩ at room
temperature.
9. Absolutely avoid crossing any signal lines over the
switching power path loop, described in the Power
Circuitry section.
Rev. A | Page 19 of 24
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