HSC-DAC-EVALCZ(Rev0) 데이터 시트보기 (PDF) - Analog Devices

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HSC-DAC-EVALCZ
(Rev.:Rev0)

10-/12-Bit, Low Power, Broadband MxFE

Analog Devices 

Table 5. Digital Logic Level Specifications

Parameter

CMOS INPUT LOGIC LEVEL

VIN Logic High

VIN Logic High

VIN Logic High

VIN Logic Low

VIN Logic Low

VIN Logic Low

CMOS OUTPUT LOGIC LEVEL

VOUT Logic High

VOUT Logic High

VOUT Logic High

VOUT Logic Low

VOUT Logic Low

VOUT Logic Low

DAC CLOCK INPUT

Differential Peak-to-Peak Voltage

Duty Cycle

Slew Rate

DIRECT CLOCKING

Clock Rate

DLL ENABLED

Clock Rate

SERIAL PERIPHERAL INTERFACE

Maximum Clock Rate

Minimum Pulse Width High (tHIGH)

Minimum Pulse Width Low (tLOW)

Setup Time, SDIO (Data In) to SCLK (tDS)

Hold Time, SDI to SCLK (tDH)

Data Valid, SDIO (Data Out) to SCLK (tDV)

Setup Time, CS to SCLK (tS)

AD9961/AD9963

Conditions

DRVDD = 1.8 V

DRVDD = 2.5 V

DRVDD = 3.3 V

DRVDD = 1.8 V

DRVDD = 2.5 V

DRVDD = 3.3 V

DRVDD = 1.8 V

DRVDD = 2.5 V

DRVDD = 3.3 V

DRVDD = 1.8 V

DRVDD = 2.5 V

DRVDD = 3.3 V

CLKP/CLKN inputs

DLL delay line output

Min

Typ

Max

Unit

1.2

V

1.7

V

2.0

V

0.5

V

0.7

V

0.8

V

1.35

V

2.05

V

2.4

V

0.4

V

0.4

V

0.4

V

200

400

CLK33V mV p-p diff

45

55

%

0.1

V/ns

0.1

200

MHz

%

100

310

MHz

50

MHz

10

ns

10

ns

5.0

ns

5.0

ns

5.0

ns

5.0

ns

Rev. 0 | Page 7 of 60

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