AD9557
SERIAL PORT SPECIFICATIONS—SPI MODE
Table 15.
Parameter
CS
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SCLK
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO
As an Input
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
As an Output
Output Logic 1 Voltage
Output Logic 0 Voltage
SDO
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
SCLK
Clock Rate, 1/tCLK
Pulse Width High, tHIGH
Pulse Width Low, tLOW
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CS to SCLK Setup (tS)
CS to SCLK Hold (tC)
CS Minimum Pulse Width High
Min
Typ
2.2
44
88
2
2.2
0.8
200
1
2
2.2
1
1
2
DVDD3 − 0.6
DVDD3 − 0.6
10
13
3
6
10
0
6
Data Sheet
Max
Unit Test Conditions/Comments
V
1.2
V
μA
μA
pF
Internal 30 kΩ pull-down resistor
V
1.2
V
μA
μA
pF
V
1.2
V
μA
μA
pF
V
1 mA load current
0.4
V
1 mA load current
V
1 mA load current
0.4
V
1 mA load current
40
MHz
ns
ns
ns
ns
10
ns
ns
ns
ns
Rev. A | Page 12 of 92