AD9510BCPZ-REEL7(RevB) 데이터 시트보기 (PDF) - Analog Devices

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AD9510BCPZ-REEL7
(Rev.:RevB)

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Analog Devices 

AD9510

CLOCK OUTPUT PHASE NOISE

Table 5.

Parameter

CLK1-TO-LVPECL ADDITIVE PHASE NOISE

CLK1 = 622.08 MHz, OUT = 622.08 MHz

Divide Ratio = 1

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

>1 MHz Offset

CLK1 = 622.08 MHz, OUT = 155.52 MHz

Divide Ratio = 4

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

>1 MHz Offset

CLK1 = 622.08 MHz, OUT = 38.88 MHz

Divide Ratio = 16

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

>1 MHz Offset

CLK1 = 491.52 MHz, OUT = 61.44 MHz

Divide Ratio = 8

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

> 1 MHz Offset

CLK1 = 491.52 MHz, OUT = 245.76 MHz

Divide Ratio = 2

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

>1 MHz Offset

CLK1 = 245.76 MHz, OUT = 61.44 MHz

Divide Ratio = 4

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

>1 MHz Offset

Data Sheet

Min Typ Max Unit

Test Conditions/Comments

Distribution Section only, does not include

PLL or external VCO/VCXO

Input slew rate > 1 V/ns

−125

−132

−140

−148

−153

−154

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

−128

−140

−148

−155

−161

−161

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

−135

−145

−158

−165

−165

−166

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

−131

−142

−153

−160

−165

−165

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

−125

−132

−140

−151

−157

−158

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

dBc/Hz

−138

−144

−154

−163

−164

−165

Rev. B | Page 8 of 56

dBc/Hz

dBc/Hz

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