AD8326ARE-EVAL 데이터 시트보기 (PDF) - Analog Devices

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AD8326ARE-EVAL

High Output Power Programmable CATV Line Driver

Analog Devices 

AD8326

PIN CONFIGURATION

Pin No.

1

2

3

4, 28

5, 9, 10, 19,

20, 23, 27

6

7

8, 12, 17

11, 13, 16, 18,

22, 24

14

15

21

25

26

DATEN 1

28 GND

SDATA 2

CLK 3

27 VCC

26 VIN–

GND 4

25 VIN+

VCC 5

24 VEE

TXEN

SLEEP

NC

6 AD8326 23 VCC

7 TOP VIEW 22 VEE

8 (Not to Scale) 21 BYP

VCC 9

20 VCC

VCC 10

19 VCC

E Mnemonic

T DATEN

E SDATA

CLK

L GND

VCC

O TXEN

SLEEP

S NC

VEE

OUT–

B OUT+

BYP

O VIN+

VEE 11

NC 12

VEE 13

OUT– 14

18 VEE

17 NC

16 VEE

15 OUT+

NC = NO CONNECT

PIN FUNCTION DESCRIPTIONS

Description

Data Enable Low Input. This port controls the 8-bit parallel data latch and shift register. A Logic

0-to-1 transition transfers the latched data to the attenuator core (updates the gain) and simulta-

neously inhibits serial data transfer into the register. A 1-to-0 transition inhibits the data latch

(holds the previous gain state) and simultaneously enables the register for serial data load.

Serial Data Input. This digital input allows for an 8-bit serial (gain) word to be loaded into the

internal register with the MSB (Most Significant Bit) first and ignored.

Clock Input. The clock port controls the serial attenuator data transfer rate to the 8-bit master-

slave register. A Logic 0-to-1 transition latches the data bit and a 1-to-0 transfers the data bit to

the slave. This requires the input serial data word to be valid at or before this clock transition.

Common External Ground Reference

Common Positive External Supply Voltage. A 0.1 µF capacitor must decouple each pin.

Transmit Enable pin. Logic 1 powers up the part.

Low Power Sleep Mode. In the Sleep mode, the AD8326’s supply current is reduced to 4 mA. A

Logic 0 powers down the part (High ZOUT State) and a Logic 1 powers up the part.

No Connection to these pins.

Common Negative External Supply Voltage. A 0.1 µF capacitor must decouple each pin.

Negative Output Signal

Positive Output Signal

Internal Bypass. This pin must be externally ac-coupled (0.1 µF capacitor).

Noninverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a

0.1 µF capacitor.

VIN–

Inverting Input. DC-biased to approximately VCC/2. Should be ac-coupled with a 0.1 µF capacitor.

–6–

REV. 0

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