AD8326ARE-EVAL 데이터 시트보기 (PDF) - Analog Devices
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AD8326ARE-EVAL Datasheet PDF : 24 Pages
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AD8326
APPLICATIONS
SPI Programming
General Applications
The AD8326 is controlled through a serial peripheral interface
The AD8326 is primarily intended for use as the upstream
(SPI) of three digital data lines, CLK, DATEN, and SDATA.
power amplifier (PA), also known as a line driver, in DOCSIS
Changing the gain requires 8 bits of data to be streamed into the
(Data Over Cable Service Interface Specification) certified
SDATA port. The sequence of loading the SDATA register
cable modems, cable telephony systems, and CATV set-top
begins on the falling edge of the DATEN pin, which activates
boxes. The upstream signal is either a QPSK or QAM signal
the CLK line. With the CLK line activated, data on the SDATA
generated by a DSP, a dedicated QPSK/QAM modulator, or a
line is clocked into the serial shift register, Most Significant Bit
DAC. In all cases the signal must be low-pass filtered before
(MSB) first, on the rising edge of the CLK pulses. Since a 7-bit
being applied to the PA in order to filter out-of-band noise and shift register is used in the AD8326, the MSB of the 8-bit word
higher order harmonics from the amplified signal. Due to the is a “don’t care” bit and is shifted out of the register on the eighth
varying distances between the cable modem and the headend, clock pulse. The data is latched into the attenuator core on the
the upstream PA must be capable of varying the output power
rising edge of the DATEN line. This provides control over the
by applying gain or attenuation. The varying output power of
the AD8326 ensures that the signal from the cable modem will
have the proper level once it arrives at the headend. The upstream
signal path also contains a transformer, a diplexer, and cable split-
ters. The AD8326 has been designed to overcome losses associated
with these passive components in the upstream cable path, particu-
E larly in modems that support cable telephony.
AD8326ARP Applications
The AD8326ARP is in a thermally enhanced PSOP2 package,
[ T ] and designed for single 12 V supply and output power applica-
tions up to +69 dBmV. The AD8326ARP will provide maximum
performance in 12 V systems.
E AD8326ARE Applications
The AD8326ARE is in a TSSOP package with an exposed ther-
mal pad. It is designed for dual ± 5 V or single 10 V supplies. For
applications requiring up to 65 dBmV of output power, lower
L cost, smaller package, and lower power dissipation, the TSSOP
package is most appropriate.
Operational Description
The AD8326 consists of four analog functions in the transmit
O enable or forward mode. The input amplifier (preamp) can be
used single-ended or differentially. If the input is used in the
differential configuration, it is imperative that the input signals be
180 degrees out of phase and of equal amplitudes. This will
S ensure proper gain accuracy and harmonic performance. The
preamp stage drives a vernier stage that provides the fine tune
gain adjustment. The approximate step resolution of 0.75 dB is
implemented in this stage and provides a total of approximately
B 5.25 dB of accumulated attenuation. After the vernier stage, a
DAC provides the bulk of the AD8326’s attenuation (8 bits or
48 dB). The signals in the preamp and vernier gain blocks are
differential to improve the PSRR and linearity. A differential
O current is fed from the DAC into the output stage, which
changes in the output signal level. The serial interface timing for
the AD8326 is shown in Figures 2 and 3. The programmable
gain range of the AD8326 is –25.75 dB to +27.5 dB with steps
of 0.75 dB. This provides a total gain range of 53.25 dB. The
AD8326 was characterized with a TOKO transformer (TOKO
#617DB-A0070), and the stated gain values include the losses
due to the transformer.
For gain codes from 0 through 71 the gain transfer function is:
AV = 27.5 dB – (0.75 dB × (71 – CODE )
where AV is the gain in dB and CODE is the decimal equivalent
of the 8-bit word. Gain codes 0 to 71 provide linear changes in
gain. Figure 4 shows the gain characteristics of the AD8326 for
all possible values in an 8-bit word. Note that maximum gain is
achieved at Code 71. From Code 72 through 127 the 5.25 dB
of attenuation from the vernier stage is being applied over every
eight codes, resulting in the saw tooth characteristic at the top
of the gain range. Because the eighth bit is shifted out of the
register, the gain characteristics for Codes 128 through 255 are
identical to Codes 0 through 127, as depicted in Figure 4.
28
21
14
7
0
–7
–14
–21
–28
0
32
64 96 128 160 192 224 256
GAIN CODE – Decimal
Figure 4. Gain Code vs. Gain
amplifies these currents to the appropriate levels necessary to
drive a 75 Ω load.
The output stage utilizes negative feedback to implement a
differential 75 Ω output impedance, which eliminates the need
for external matching resistors needed in typical video (or
video filter) termination requirements.
–10–
REV. 0
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