AD7631BCPZ 데이터 시트보기 (PDF) - Analog Devices
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AD7631BCPZ Datasheet PDF : 32 Pages
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AD7631
Data Sheet
Table 4. Serial Clock Timings in Master Read After Convert Mode
DIVSCLK[1]
0
0
1
1
DIVSCLK[0]
Symbol
0
1
0
1
Unit
SYNC to SDCLK First Edge Delay Minimum
Internal SDCLK Period Minimum
Internal SDCLK Period Maximum
Internal SDCLK High Minimum
Internal SDCLK Low Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SDCLK Last Edge to SYNC Delay Minimum
BUSY High Width Maximum
t18
3
20
20
20
ns
t19
30
60
120
240
ns
t19
45
90
180
360
ns
t20
15
30
60
120
ns
t21
10
25
55
115
ns
t22
4
20
20
20
ns
t23
5
8
35
90
ns
t24
5
7
35
90
ns
t28
2.55
3.40
5.00
8.20
µs
1.6mA
IOL
TO OUTPUT
PIN CL
60pF
1.4V
500µA
IOH
NOTES
1. IN SERIAL INTERFACE MODES, THE SYNC, SDCLK,
AND SDOUT ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
Figure 2. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, and SDCLK Outputs, CL = 10 pF
0.8V
tDELAY
2V
0.8V
2V
tDELAY
2V
0.8V
Figure 3. Voltage Reference Levels for Timing
Rev. B | Page 6 of 32
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