AD73411 데이터 시트보기 (PDF) - Analog Devices

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AD73411

Low-Power Analog Front End with DSP Microcomputer

Analog Devices 

AD73411

ANTIALIAS

FILTER

100⍀

0.047␮F

0.047␮F

100⍀

VINP

VINN

0/38dB

PGA

VREF

VOUTP

VOUTN

REFOUT

REFCAP

0.1␮F

+6/–15dB

PGA

CONTINUOUS

TIME

LOW-PASS

FILTER

REFERENCE

AD73411

Figure 25. Analog Input (DC-Coupled)

Analog Inputs

The analog input (encoder) section of the AD73411 can be inter-

faced to external circuitry in either ac-coupled or dc-coupled modes.

It is also possible to drive the ADC in either differential or

single-ended modes. If the single-ended mode is chosen it is

possible, using software control, to multiplex between two single-

ended inputs connected to the positive and negative input pins.

The primary concerns in interfacing to the ADC are to provide

adequate antialias filtering and to ensure that the signal source

will drive the switched-capacitor input of the ADC correctly.

The sigma-delta design of the ADC and its oversampling char-

acteristics simplify the antialias requirements, but it must be

remembered that the single-pole RC filter is primarily intended

to eliminate aliasing of frequencies above the Nyquist frequency of

the sigma-delta modulator’s sampling rate (typically 2.048 MHz).

It may still require a more specific digital filter implementa-

tion in the DSP to provide the final signal frequency response

characteristics. It is recommended that for optimum performance

the capacitors used for the antialiasing filter be of high quality

dielectric (NPO). The second issue mentioned above is interfacing

the signal source to the ADC’s switched capacitor input load.

The SC input presents a complex dynamic load to a signal

source, therefore, it is important to understand that the slew

rate characteristic is an important consideration when choosing

external buffers for use with the AD73411.

The AD73411’s on-chip 38 dB preamplifier can be enabled

when there is not enough gain in the input circuit; the preampli-

fier is configured by bits IGS0–2 of CRD. The total gain must be

configured to ensure that a full-scale input signal produces a signal

level at the input to the sigma-delta modulator of the ADC that

does not exceed the maximum input range.

The dc biasing of the analog input signal is accomplished with

an on-chip voltage reference. If the input signal is not biased at

the internal reference level (via REFOUT), it must be ac-coupled

with external coupling capacitors. CIN should be 0.1 µF or larger.

The dc biasing of the input can then be accomplished using

resistors to REFOUT as in Figures 27 through 29.

VINP

VINN

OPTIONAL

BUFFER

VOUTP

VOUTN

REFOUT

REFCAP

0.1␮F

0/38dB

PGA

VREF

+6/–15dB

PGA

CONTINUOUS

TIME

LOW-PASS

FILTER

REFERENCE

AD73411

Figure 26. Analog Input (DC-Coupled) Using External

Amplifiers

The AD73411’s ADC inputs are biased about the internal refer-

ence level (REFCAP level), therefore, it may be necessary to bias

external signals to this level using the buffered REFOUT level

as the reference. This is applicable in either dc- or ac-coupled

configurations. In the case of dc coupling, the signal (biased

to REFOUT) may be applied directly to the inputs as shown in

Figure 25, or it may be conditioned in an external op amp where

it can also be biased to the reference level using the buffered

REFOUT signal as shown in Figure 26.

In the case of ac-coupling, a capacitor is used to couple the

signal to the input of the ADC. The ADC input must be biased

to the internal reference (REFCAP) level, which is done by

connecting the input to the REFOUT pin through a 10 kΩ

resistor as shown in Figure 27.

0.1␮F 100⍀

0.1␮F 10k⍀

100⍀

10k⍀

VINP

0.047␮F

VINN

0.047␮F

0/38dB

PGA

VREF

VOUTP

VOUTN

REFOUT

REFCAP

0.1␮F

+6/–15dB

PGA

CONTINUOUS

TIME

LOW-PASS

FILTER

REFERENCE

AD73411

Figure 27. Analog Input (AC-Coupled) Differential

If the ADC is being connected in single-ended mode, the

AD73411 should be programmed for single-ended mode using

the SEEN and INV bits of CRF, and the inputs connected as

shown in Figure 28. When operated in single-ended input mode,

the AD73411 can multiplex one of the two inputs to the ADC

input, as shown in Figures 28 and 29.

–32–

REV. 0

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