EVAL-AD7264EDZ(RevD) 데이터 시트보기 (PDF) - Analog Devices

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EVAL-AD7264EDZ
(Rev.:RevD)

1 MSPS, 14-Bit, Simultaneous Sampling SAR ADC with PGA and Four Comparators

Analog Devices 

Data Sheet

AD7264

CS

SCLK

DOUTA

DOUTB

FIRST DATA BIT CLOCKED

OUT ON THIS EDGE

FIRST DATA BIT READ

ON THIS EDGE

t2

1

2

3

4

THREE-STATE

THREE-STATE

t8

5

18

19

20

21

22

31

32

33

t4

t5

DB13A DB12A DB11A

DB13B DB12B DB11B

DB1A

DB1B

DB0A

DB0B

THREE-

STATE

THREE-

STATE

Figure 35. Serial Interface Timing Diagram When Reading Data on the Rising SCLK Edge with VDRIVE = 3 V

Rev. D | Page 25 of 29

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