EVAL-AD7091SDZ 데이터 시트보기 (PDF) - Analog Devices
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EVAL-AD7091SDZ Datasheet PDF : 20 Pages
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AD7091
Data Sheet
Parameter
Power Dissipation
Normal Mode—Static4
Normal Mode—Operational
Power-Down Mode
Test Conditions/Comments
VDD = 3 V
VDD = 3 V, TA = −40°C to +85°C
VIN = 0 V
VDD = 5.25 V
VDD = 3 V
VDD = 5.25 V, fSAMPLE = 1 MSPS
VDD = 3 V, fSAMPLE = 1 MSPS
VDD = 5.25 V
VDD = 3 V
Min
Typ
Max
Unit
0.324
8
µA
0.324
1.8
µA
50
142
µW
27
84
µW
2.4
3
mW
1.1
1.4
mW
2
44
µW
1
24
µW
1 Dynamic performance is achieved when SCLK operates in burst mode. Operating a free running SCLK during the acquisition phase degrades dynamic performance.
2 See the Terminology section.
3 Sample tested during initial release to ensure compliance.
4 SCLK is operating in burst mode and CS is idling high. With a free running SCLK and CS pulled low, the IDD static current is increased by 60 µA typical at VDD = 5.25 V.
TIMING SPECIFICATIONS
VDD = 2.09 V to 5.25 V, TA = −40°C to +125°C, unless otherwise noted. Signals are specified from 10% to 90% of VDD with a load
capacitance of 12 pF on the output pin.1
Table 2.
Parameter
fSCLK
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
tQUIET
Limit at TMIN, TMAX
50
8
7
0.4 tSCLK
3
0.4 tSCLK
15
10
650
6
18
8
8
100
50
Unit
MHz max
ns max
ns max
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns min
ns min
µs max
ns min
Description
Frequency of serial read clock
Delay from the end of a conversion until SDO exits the three-state condition
Data access time after SCLK falling edge
SCLK high pulse width
SCLK to data valid hold time
SCLK low pulse width
SCLK falling edge to SDO high impedance
CONVST pulse width
Conversion time
CS low time before the end of a conversion
Delay from CS falling edge until SDO exits the three-state condition
CS high time before the end of a conversion
Delay from the end of a conversion until the CS falling edge
Power-up time
Time between the last SCLK edge and the next CONVST pulse
1 Sample tested during initial release to ensure compliance.
Rev. B | Page 4 of 20
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