AD5790
5
VDD = +15V
VSS = –15V
3 AD8675 OUTPUT BUFFER
±10V SPAN
+10V SPAN
+5V SPAN
1
–1
–3
–5
–7
–9
–11
–40 –20
0
20
40
60
80
100
TEMPERATURE (°C)
Figure 35. Zero-Scale Error vs. Temperature
0
VDD = +15V
VSS = –15V
–2 AD8675 OUTPUT BUFFER
±10V SPAN
+10V SPAN
+5V SPAN
–4
–6
–8
–10
–12
–14
–16
–40 –20
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 36. Gain Error vs. Temperature
900
TA = 25°C
800
700
600
500
IOVCC = 5V, LOGIC VOLTAGE
INCREASING
IOVCC = 5V, LOGIC VOLTAGE
DECREASING
IOVCC = 3V, LOGIC VOLTAGE
INCREASING
IOVCC = 3V, LOGIC VOLTAGE
DECREASING
400
300
200
100
0
0
1
2
3
4
5
6
LOGIC INPUT VOLTAGE (V)
Figure 37. IOICC vs. Logic Input Voltage
Data Sheet
0.010
0.008
IDD
0.006
0.004
0.002
0
–0.002
–0.004
–0.006
ISS
–0.008
–0.010
–20 –15 –10
–5
0
5
VDD/VSS (V)
10
15
20
Figure 38. Power Supply Currents vs. Power Supply Voltages
6
4
2
0
–2
–4
–6
–8
–10
–1
0
1
2
3
4
5
TIME (µs)
Figure 39. Rising Full-Scale Voltage Step
6
4
2
0
–2
–4
–6
–8
–10
–1
0
1
2
3
4
5
TIME (µs)
Figure 40. Falling Full-Scale Voltage Step
Rev. E | Page 14 of 27