AD5697RBRUZ-RL7 데이터 시트보기 (PDF) - Analog Devices

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AD5697RBRUZ-RL7

Dual, 12-Bit nanoDAC+ with 2 ppm/°C Reference, I2C Interface

Analog Devices 

AD5697R

Data Sheet

LOAD DAC (HARDWARE LDAC PIN)

The AD5697R DACs have double buffered interfaces consisting

of two banks of registers: input registers and DAC registers. The

user can write to any combination of the input registers. Updates to

the DAC register are controlled by the LDAC pin.

OUTPUT

AMPLIFIER

VREF

12-BIT

DAC

VOUT

LDAC

DAC

REGISTER

INPUT

REGISTER

SCL

SDO

INPUT SHIFT

REGISTER

Figure 46. Simplified Diagram of Input Loading Circuitry for a Single DAC

Instantaneous DAC Updating (LDAC Held Low)

LDAC is held low while data is clocked into the input register

using Command 0001. Both the addressed input register and

the DAC register are updated on the 24th clock, and the output

begins to change (see Table 14).

Deferred DAC Updating (LDAC is Pulsed Low)

LDAC is held high while data is clocked into the input register

using Command 0001. Both DAC outputs are asynchronously

updated by taking LDAC low after the 24th clock. The update

then occurs on the falling edge of LDAC.

LDAC MASK REGISTER

Command 0101 is reserved for this software LDAC mask function,

which allows the address bits to be ignored. Writing to the DAC

using Command 0101 loads the 4-bit LDAC register (DB3 to DB0).

The default for each channel is 0; that is, the LDAC pin works

normally. Setting the bits to 1 forces this DAC channel to ignore

transitions on the LDAC pin, regardless of the state of the

hardware LDAC pin. This flexibility is useful in applications where

the user wishes to select which channels respond to the LDAC

pin.

Table 12. LDAC Overwrite Definition

Load LDAC Register

LDAC Bits

(DB3 or DB0)

0

1

LDAC Pin

1 or 0

X1

LDAC Operation

Determined by the LDAC pin.

DAC channels update and

override the LDAC pin. DAC

channels see LDAC pin as 1.

1 X = don’t care.

The LDAC register gives the user extra flexibility and control over

the hardware LDAC pin (see Table 12). Setting the LDAC bits

(DB3 or DB0) to 0 for a DAC channel means that the update of the

channel is controlled by the hardware LDAC pin.

Table 13. 24-Bit Input Shift Register Contents for LDAC Operation1

DB23

(MSB)

DB22 DB21 DB20 DB19 DB18 DB17 DB16

0

0

0

1

X

X

X

X

Command bits (C3 to C0)

Address bits,

don’t care

1 X = don’t care.

DBB15 to DB4

X

Don’t care

DB0

DB3

DB2 DB1 (LSB)

DAC B

0

0

DAC A

Setting LDAC to 1 overrides

the LDAC pin

Table 14. Write Commands and LDAC Pin Truth Table1

Command Description

0001

Write to Input Register n (dependent on LDAC)

0010

0011

Update DAC Register n with contents of

Input Register n

Write to and update DAC Channel n

Hardware LDAC

Pin State

VLOGIC

GND 2

VLOGIC

GND

VLOGIC

GND

Input Register

Contents

Data update

Data update

No change

No change

Data update

Data update

DAC Register Contents

No change (no update)

Data update

Updated with input register contents

Updated with input register contents

Data update

Data update

1 A high-to-low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked

(blocked) by the LDAC mask register.

2 When the LDAC pin is permanently tied low, the LDAC mask bits are ignored.

Rev. B | Page 22 of 27

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