AD5172 데이터 시트보기 (PDF) - Analog Devices
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AD5172 Datasheet PDF : 28 Pages
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Data Sheet
TIMING CHARACTERISTICS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter
I2C INTERFACE TIMING CHARACTERISTICS1
SCL Clock Frequency
Bus-Free Time Between Stop and Start, tBUF
Hold Time (Repeated Start), tHD;STA
Low Period of SCL Clock, tLOW
High Period of SCL Clock, tHIGH
Setup Time for Repeated Start Condition, tSU;STA
Data Hold Time, tHD;DAT2
Data Setup Time, tSU;DAT
Fall Time of Both SDA and SCL Signals, tF
Rise Time of Both SDA and SCL Signals, tR
Setup Time for Stop Condition, tSU;STO
OTP Program Time
Symbol Conditions
fSCL
t1
t2
After this period, the first clock
pulse is generated.
t3
t4
t5
t6
t7
t8
t9
t10
t11
1 See the timing diagrams for the locations of measured values (that is, see Figure 3 and Figure 48 to Figure 51).
2 The maximum tHD;DAT has to be met only if the device does not stretch the low period (tLOW) of the SCL signal.
Timing Diagram
SCL
t2
SDA
t1
P
S
t8
t6
t9
t3
t4
t7
t8
t9
t2
t5
S
Figure 3. I2C Interface Detailed Timing Diagram
AD5172/AD5173
Min Typ Max Unit
400 kHz
1.3
μs
0.6
μs
1.3
μs
0.6
μs
0.6
μs
0.9 μs
100
ns
300 ns
300 ns
0.6
μs
400
ms
t10
P
Rev. I | Page 7 of 28
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