AD5173BRM10(RevA) 데이터 시트보기 (PDF) - Analog Devices

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AD5173BRM10
(Rev.:RevA)

256-Position One-Time Programmable Dual-Channel I2C Digital Potentiometers

Analog Devices 

SCL

t2

SDA

t1

P

S

t8

t6

t9

t3

t4

t7

t8

t9

t2

t5

S

Figure 49. I2C Interface Detailed Timing Diagram

AD5172/AD5173

t10

P

SCL

SDA

START BY

MASTER

1

91

91

9

01 0111

FRAME 1

SLAVE ADDRESS BYTE

1 R/W

A0 SD T 0 OW X X

ACK BY

AD5172

FRAME 2

INSTRUCTION BYTE

X

D7 D6 D5 D4 D3 D2 D1 D0

ACK BY

AD5172

ACK BY

AD5172

FRAME 3

DATA BYTE

STOP BY

MASTER

Figure 50. Writing to the RDAC Register—AD5172

SCL

SDA

START BY

MASTER

1

91

91

9

0 1 0 1 1 AD1 AD0 R/W

A0 SD T 0 OW X X

FRAME 1

SLAVE ADDRESS BYTE

ACK BY

AD5173

FRAME 2

INSTRUCTION BYTE

X

D7 D6 D5 D4 D3 D2 D1 D0

ACK BY

AD5173

ACK BY

AD5173

FRAME 3

DATA BYTE

STOP BY

MASTER

Figure 51. Writing to the RDAC Register—AD5173

SCL

SDA

START BY

MASTER

1

91

91

9

0 1 0 1 1 1 1 R/W

D7 D6 D5 D4 D3 D2 D1 D0

E1 E0 X X X X X X

ACK BY

AD5172

ACK BY

MASTER

NO ACK

BY MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

STOP BY

MASTER

Figure 52. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5172

SCL

SDA

START BY

MASTER

1

91

91

9

0 1 0 1 1 AD1 AD0 R/W

D7 D6 D5 D4 D3 D2 D1 D0

E1 E0 X X X X X X

ACK BY

AD5173

ACK BY

MASTER

NO ACK

BY MASTER

FRAME 1

SLAVE ADDRESS BYTE

FRAME 2

INSTRUCTION BYTE

FRAME 3

DATA BYTE

STOP BY

MASTER

Figure 53. Reading Data from a Previously Selected RDAC Register in Write Mode—AD5173

Rev. A | Page 19 of 24

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