AD1871YRS-REEL 데이터 시트보기 (PDF) - Analog Devices
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AD1871YRS-REEL Datasheet PDF : 28 Pages
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AD1871
DATA INTERFACE TIMING (STANDALONE MODE–SLAVE)
Mnemonic
tBCH
tBCL
tBDSD
tLRS
tLRH
Description
BCLK High Width
BCLK Low Width
DOUT Delay
LRCLK Setup
LRCLK Hold
Min
Typ
30
30
20
10
5
BCLK
LRCLK
DOUT
LEFT-JUSTIFIED
MODE
tBCH
tLRS
tDBP
tBCL
tBDSD
MSB
MSB–1
Max
Unit
ns
ns
ns
ns
ns
DOUT
I2S-JUSTIFIED
MODE
MSB
DOUT
RIGHT-JUSTIFIED
MODE
MSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 3. Slave Data Interface Timing
Comment
From BCLK Falling
To BCLK Rising
From BCLK Rising
LSB
–6–
REV. 0
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