AD1871YRS-REEL 데이터 시트보기 (PDF) - Analog Devices
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AD1871YRS-REEL Datasheet PDF : 28 Pages
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DATA INTERFACE TIMING (STANDALONE MODE–MASTER)
Mnemonic
tBDLY
tBLDLY
tBDDLY
Description
BCLK Delay
LRCLK Delay to Low
DOUT Delay
Min
Typ
Max
20
10
10
Unit
ns
ns
ns
Comment
From MCLK Rising
From BCLK Falling
From BCLK Falling
AD1871
MCLK
tBDLY
BCLK
tBLDLY
LRCLK
DOUT
LEFT-JUSTIFIED
MODE
tBDDLY
MSB
MSB–1
DOUT
I2S-JUSTIFIED
MODE
MSB
DOUT
RIGHT-JUSTIFIED
MODE
MSB
LSB
8-BIT CLOCKS
(24-BIT DATA)
12-BIT CLOCKS
(20-BIT DATA)
16-BIT CLOCKS
(16-BIT DATA)
Figure 2. Master Data Interface Timing
REV. 0
–5–
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