A6812 데이터 시트보기 (PDF) - Allegro MicroSystems
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A6812 Datasheet PDF : 9 Pages
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A6812
DABiC-IV 20-Bit Serial-Input
Latched Source Driver
TIMING REQUIREMENTS and SPECIFICATIONS
(Logic Levels are VDD and Ground)
C
CLOCK
50%
SERIAL
DATA IN
SERIAL
DATA OUT
A
B
DATA
50%
t p(CH-SQX)
50%
D
E
DATA
STROBE
50%
BLANKING
OUT N
LOW = ALL OUTPUTS ENABLED
t p(STH-QH)
t p(STH-QL)
90%
DATA
10%
BLANKING
OUT N
Dwg. WP-029
HIGH = ALL OUTPUTS BLANKED (DISABLED)
50%
t en(BQ)
t dis(BQ)
tr
DATA
10%
tf
90%
50%
A. Data Active Time Before Clock Pulse
(Data Set-Up Time), tsu(D) ........................................ 25 ns
B. Data Active Time After Clock Pulse
(Data Hold Time), th(D) ............................................. 25 ns
C. Clock Pulse Width, tw(CH) .............................................. 50 ns
D. Time Between Clock Activation and Strobe, tsu(C) ...... 100 ns
E. Strobe Pulse Width, tw(STH) ........................................... 50 ns
NOTE – Timing is representative of a 10 MHz clock. Higher
speeds may be attainable with increased supply voltage; op-
eration at high temperatures will reduce the specified maximum
clock frequency.
Serial Data present at the input is transferred to the shift
register on the logic “0” to logic “1” transition of the CLOCK
input pulse. On succeeding CLOCK pulses, the registers shift
Dwg. WP-030A
data information towards the SERIAL DATA OUTPUT. The
SERIAL DATA must appear at the input prior to the rising edge
of the CLOCK input waveform.
Information present at any register is transferred to the re-
spective latch when the STROBE is high (serial-to-parallel con-
version). The latches will continue to accept new data as long
as the STROBE is held high. Applications where the latches are
bypassed (STROBE tied high) will require that the BLANKING
input be high during serial data entry.
When the BLANKING input is high, the output source driv-
ers are disabled (OFF); the pnp active pull-down sink drivers are
ON. The information stored in the latches is not affected by the
BLANKING input. With the BLANKING input low, the outputs
are controlled by the state of their respective latches.
Allegro MicroSystems, Inc.
7
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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