A6810SLW-T 데이터 시트보기 (PDF) - Allegro MicroSystems

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A6810SLW-T

10-Bit Serial Input Latched Source Driver

Allegro MicroSystems 

A6810

10-Bit Serial Input Latched Source Driver

Package A 18-Pin DIP

22.86 ±0.51

18

A

12

2.54

1.52

+0.25

–0.38

0.46 ±0.12

6.35

+0.76

–0.25

10.92

+0.38

–0.25

0.25

+0.10

–0.05

7.62

5.33 MAX SEATING C

PLANE

3.30

+0.51

–0.38

All dimensions nominal, not for tooling use

(reference JEDEC MS-001 AC)

Dimensions in inches

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

A Terminal #1 mark area

12.80±0.20

20

Package LW 20-Pin SOICW

4° ±4

20

0.27

+0.07

–0.06

2.25

7.50±0.10 10.30±0.33

A

12

20X

0.10 C

0.41 ±0.10

C

SEATING

PLANE

1.27

2.65 MAX

0.20 ±0.10

For Reference Only

Dimensions in millimeters

(Reference JEDEC MS-013 AC)

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

9.50

0.84

+0.44

–0.43

12

0.65

1.27

0.25

SEATING PLANE

GAUGE PLANE

B PCB Layout Reference View

A Terminal #1 mark area

B Reference pad layout (reference IPC SOIC127P1030X265-20M)

All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary

to meet application process requirements and PCB layout tolerances

Allegro MicroSystems, Inc.

7

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

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