
Mode Select Table
Action on the Rising
PE CET CEP
MR
Clock Edge ( )
L
X X X Reset (Clear)
H
L X X Load (Pn→Qn)
H
H H H Count (Increment)
H
H L X No Change (Hold)
H
HX
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
L No Change (Hold)
Block Diagram
State Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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