74VCX16835 데이터 시트보기 (PDF) - Fairchild Semiconductor
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74VCX16835
Fairchild Semiconductor
74VCX16835 Datasheet PDF : 10 Pages
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Connection Diagrams
Pin Assignment for TSSOP
Pin Assignment for FBGA
(Top Thru View)
Pin Descriptions
Pin Names
OE
LE
CLK
I1 - I18
O1 - O18
NC
Description
Output Enable Input (Active LOW)
Latch Enable Input
Clock Input
Data Inputs
3-STATE Outputs
No Connect
FBGA Pin Assignments
1
2
3
4
5
6
A
O2
O1
NC GND I1
I2
B
O4
O3
NC NC
I3
I4
C
O6
O5
VCC VCC
I5
I6
D
O8
O7 GND GND I7
I8
E
O10 O9 GND GND I9
I10
F
O12 O11 GND GND I11
I12
G
O14 O13 VCC VCC
I13
I14
H
O16 O15 OE CLK I15
I16
J
O17 O18 LE GND I18
I17
Truth Table
Inputs
Outputs
OE
LE
CLK
In
On
H
X
X
X
Z
L
H
X
L
L
L
H
X
H
H
L
L
↑
L
L
L
L
↑
H
H
L
L
H
X
O0 (Note 4)
L
L
L
X
O0 (Note 5)
H = Logic HIGH
L = Logic LOW
X = Don’t Care, but not floating
Z = High Impedance
↑ = LOW-to-HIGH Clock Transition
Note 4: Output level before the indicated steady-state input conditions
were established provided that CLK was HIGH before LE went LOW.
Note 5: Output level before the indicated steady-state input conditions
were established.
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