Philips Semiconductors
Hex D-type flip-flop with reset; positive-edge trigger
AC WAVEFORMS
Product specification
74HC/HCT174
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.6
Waveforms showing the clock (CP) to output
(Qn) propagation delays, the clock pulse
width, the output transition times and the
maximum clock pulses frequency.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
Fig.7
Waveforms showing the master reset (MR)
pulse width, the master reset to output (Qn)
propagation delays and the master reset to
clock (CP) removal time.
(1) HC : VM = 50%; VI = GND to VCC.
HCT : VM = 1.3 V; VI = GND to 3 V.
The shaded areas indicate when the input is permitted to
change for predictable output performance
Fig.8 Waveforms showing the data set-up and hold times for the data input (Dn).
1998 Jul 08
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