74F273 데이터 시트보기 (PDF) - Fairchild Semiconductor

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74F273

Octal D-Type Flip-Flop

Fairchild Semiconductor 

Unit Loading/Fan Out

Pin Names

Description

D0–D7

MR

CP

Q0–Q7

Data Inputs

Master Reset (Active LOW)

Clock Pulse Input (Active Rising Edge)

Data Outputs

Mode Select-Function Table

U.L.

HIGH/LOW

1.0/1.0

1.0/1.0

1.0/1.0

50/33.3

Input IIH/IIL

Output IOH/IOL

20 µA/−0.6 mA

20 µA/−0.6 mA

20 µA/−0.6 mA

−1 mA/20 mA

Operating Mode

Inputs

Output

MR

CP

Dn

Qn

Reset (Clear)

Load “1”

Load “0”

L

H

X

X

h

L

H

H



l

L

H = HIGH Voltage Level steady state

h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock transition

L = LOW Voltage Level steady state

I = LOW Voltage Level one setup time prior to the LOW-to-HIGH clock transition

X = Immaterial

= LOW-to-HIGH clock transition

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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