74F169 데이터 시트보기 (PDF) - Philips Electronics

부품명

상세내역

제조사

74F169

4-bit up/down binary synchronous counter

Philips Electronics 

Philips Semiconductors

4-bit up/down binary synchronous counter

Product specification

74F169

FEATURES

• Synchronous counting and loading

• Up/Down counting

• Modulo 16 binary counter

• Two Count Enable inputs for n-bit cascading

• Positive edge-triggered clock

• Built-in carry look-ahead capability

• Presettable for programmable operation

DESCRIPTION

The 74F169 is a 4-bit synchronous, presettable Modulo 16 up/down

counter featuring an internal carry look-ahead for applications in

high-speed counting designs. Synchronous operation is provided by

having all flip-flops clocked simultaneously so that the outputs

change coincident with each other when instructed by the Count

Enable inputs and internal gating. This mode of operation eliminates

the output spikes which are normally associated with asynchronous

(ripple clock) counters. A buffered clock input triggers the flip-flops

on the Low-to-High transition of the clock.

The counter is fully programmable; that is, the outputs may be

preset to either level.

Presetting is synchronous with the clock and takes place regardless

of the levels of the Count Enable inputs. A Low level on the Parallel

Enable (PE) input disables the counter and causes the data at the

Dn input to be loaded into the counter on the next Low-to-High

transition of the clock.

The direction of counting is controlled by the Up/Down (U/D) input; a

High will cause the count to increase, a Low will cause the count to

decrease.

The carry look-ahead circuitry provides for n-bit synchronous

applications without additional gating. Instrumental in accomplishing

this function are two Count Enable inputs (CET, CEP) and a

Terminal Count (TC) output. Both Count Enable inputs must be Low

to count. The CET input is fed forward to enable the TC output. The

TC output thus enabled will produce a Low output pulse with a

duration approximately equal to the High level portion of the Q0

output. The Low level TC pulse is used to enable successive

cascaded stages.

PIN CONFIGURATION

U/D 1

CP 2

D0 3

D1 4

D2 5

D3 6

CEP 7

GND 8

16 VCC

15 TC

14 Q0

13 Q1

12 Q2

11 Q3

10 CET

9 PE

SF00766

TYPE

74F169

TYPICAL fMAX

115MHz

TYPICAL

SUPPLY CURRENT

(TOTAL)

35mA

ORDERING INFORMATION

ORDER CODE

DESCRIPTION

COMMERCIAL RANGE

VCC = 5V ±10%,

Tamb = 0°C to +70°C

16-pin plastic DIP

N74F169N

16-pin plastic SO

N74F169D

PKG

DWG #

SOT38-4

SOT109-1

INPUT AND OUTPUT LOADING AND FAN-OUT TABLE

PINS

DESCRIPTION

74F(U.L.)

HIGH/LOW

D0 - D3

CEP

Parallel data inputs

Count Enable parallel input (active Low)

1.0/1.0

1.0/1.0

CET

Count Enable Trickle input (active Low)

1.0/2.0

CP

Clock input (active rising edge)

1.0/1.0

PE

Parallel Enable input (active Low)

1.0/1.0

U/D

Up/Down count control input

1.0/1.0

Q0 - Q3

Flip-flop outputs

50/33

TC

Terminal count output (active Low)

50/33

NOTE: One (1.0) FAST Unit Load (U.L.) is defined as: 20µA in the High state and 0.6mA in the Low state.

LOAD VALUE

HIGH/LOW

20µA/0.6mA

20µA/0.6mA

20µA/1.2mA

20µA/0.6mA

20µA/0.6mA

20µA/0.6mA

1.0mA/20mA

1.0mA/20mA

1996 Jan 05

2

853–0350 16190

Share Link: