Philips Semiconductors
Latch/flip-flop
Product specification
74ALS563A/74ALS564A
LOGIC DIAGRAM – 74ALS564A
D0
D1
D2
D3
D4
D5
2
3
4
5
6
7
D6
D7
8
9
CP 11
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
D
CP Q
1
OE
VCC = Pin 20
GND = Pin 10
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
SC00117
FUNCTION TABLE – 74ALS564A
INPUTS
OE
CP
Dn
OUTPUTS
REGISTER
INTERNAL
Q0 – Q7
L
↑
l
L
H
L
↑
h
H
L
L
↑
X
NC
NC
H
↑
X
NC
Z
H
↑
Dn
Dn
Z
H=
h=
L=
l=
NC=
X=
Z=
↑=
↑=
High voltage level
High state must be present one setup time before the Low-to-High clock transition
Low voltage level
Low state must be present one setup time before the Low-to-High clock transition
No change
Don’t care
High impedance “off ” state
Low-to-High clock transition
Not Low-to-High clock transition
OPERATING MODE
Load and read register
Hold
Disable outputs
ABSOLUTE MAXIMUM RATINGS
(Operation beyond the limit set forth in this table may impair the useful life of the device.
Unless otherwise noted these limits are over the operating free-air temperature range.)
SYMBOL
PARAMETER
VCC
VIN
IIN
VOUT
IOUT
Tamb
Tstg
Supply voltage
Input voltage
Input current
Voltage applied to output in High output state
Current applied to output in Low output state
Operating free-air temperature range
Storage temperature range
RATING
–0.5 to +7.0
–0.5 to +7.0
–30 to +5
–0.5 to VCC
48
0 to +70
–65 to +150
UNIT
V
V
mA
V
mA
°C
°C
1996 Jul 01
5