74ALS377 데이터 시트보기 (PDF) - Philips Electronics
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74ALS377 Datasheet PDF : 10 Pages
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Philips Semiconductors
Octal D flip-flop with enable
Product specification
74ALS377
FEATURES
• Ideal for addressable register applications
• Enable for address and data synchronization applications
• Eight edge-triggered D-type flip-flops
• Buffered common clock
• See 74ALS273 for master reset version
• See 74ALS373 for transparent latch version
• See 74ALS374 for 3-State version
DESCRIPTION
The 74ALS377 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered clock (CP)
input loads all flip-flops simultaneously when the Enable (E) is Low.
The register is fully edge-triggered. The state of each D input, one
setup time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output. The E input must be stable
one setup time prior to the Low-to-High clock transition for
predictable operation.
TYPE
74ALS377
TYPICAL fMAX
95MHz
TYPICAL
SUPPLY CURRENT
(TOTAL)
15mA
PIN CONFIGURATION
E1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
SF00350
ORDERING INFORMATION
ORDER CODE
DESCRIPTION
COMMERCIAL RANGE
VCC = 5V ±10%,
Tamb = 0°C to +70°C
20-pin plastic DIP
74ALS377N
20-pin plastic SOL
74ALS377D
20-pin plastic SSOP
Type II
74ALS377DB
DRAWING
NUMBER
SOT146-1
SOT163-1
SOT339-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
74ALS (U.L.)
HIGH/LOW
D0 – D7
Data inputs
1.0/2.0
CP
Clock pulse input (active rising edge)
1.0/1.0
E
Latch enable input
1.0/1.0
Q0 – Q7
Data outputs
130/240
NOTE: One (1.0) ALS unit load is defined as: 20µA in the High state and 0.1mA in the Low state.
LOGIC SYMBOL
IEC/IEEE SYMBOL
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11
CP
1
E
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC = Pin 20
GND = Pin 10
2 5 6 9 12 15 16 19
SF00351
1
G1
11
1C2
3
2D
4
7
8
13
14
17
18
LOAD VALUE
HIGH/LOW
20µA/0.2mA
20µA/0.1mA
20µA/0.1mA
2.6mA/24mA
2
5
6
9
12
15
16
19
SF00352
1991 Feb 08
2
853–1399 01670
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