68HC05BD2 데이터 시트보기 (PDF) - Freescale Semiconductor

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68HC05BD2

SPECIFICATION REV 2.0 (General Release)

Freescale Semiconductor 

GENERAL RELEASE SPEFCrIeFeICsAcTaIOlNe Semiconductor, MInCc68. HC05BD7 Rev. 2.0

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

PB0

PB1

PB2*

PB3*

PB4*

PB5*

PC0*/PWM8*

PC1*/PWM9*

PC2/PWM10/ADC0

PC3/PWM11/ADC1

PC4/PWM12/ADC2

PC5/PWM13/ADC3

PC6/PWM14/VSYNO

PC7/PWM15/HSYNO

VDD

PWM0**

VSS

Pulse

PORT DATA

A

DIR

EXTAL XTAL

OSCILLATOR

RESET IRQ/VPP

CORE

Width

Modulation

(PWM)

REG REG

AND DIVIDE

TIMER

BY 2

(COP)

ARY PORT

B

IMIN REG

DATA

DIR

REG

CPU CONTROL

ALU

68HC05 CPU

CPU REGISTERS

ACCUM

INDEX REG

0 0 0 0 0 0 0 0 1 1 STK PTR

PROGRAM COUNTER

COND CODE REG 1 1 1 H I N Z C

6-bit ADC

DDC12AB

DATA PORT

DIR D

REG REG

EL PORT DATA

R C DIR

PREG REG

5.75K-bytes ROM for

HC05BD2

11.75K-bytes ROM

RAM

256 bytes for HC05BD2

SYNC

PROCESSOR

for HC05BD7

384 bytes for HC05BD7

11.5K-bytes EPROM 384 bytes for HC705BD7

for HC705BD7

PWM1**

PWM2**

PWM3**

PWM4**

PWM5**

PWM6**

PWM7**

PD0*/SDA*

PD1*/SCL*

PD2***/CLAMP

PD3*/SOG

HSYNC

VSYNC

***: +5V open-drain

**: +5V open-drain option

*: +12V open-drain

IRQ/VPP: VPP valid for HC705 version only, not used for HC05 version

Figure 1-1: MC68HC05BD7 Block Diagram

Page 4

SECTION 1: GENERAL DESCRIPTION

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