68HC05BD2 데이터 시트보기 (PDF) - Freescale Semiconductor
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68HC05BD2 Datasheet PDF : 85 Pages
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MC68HC05BD7 RevF. 2r.e0escale SemicondGuEcNtoERr,AILnRcE.LEASE SPECIFICATION
SECTION 1
GENERAL DESCRIPTION
The MC68HC05BD7 HCMOS microcontroller is a member of the M68HC05 Family of low-
cost single-chip microcontrollers. It is particularly suitable as multi-sync computer monitor
controller. This 8-bit microcontroller unit (MCU) contains an on-chip oscillator, CPU, RAM,
ROM, DDC12AB module, parallel I/O, Pulse Width Modulator, Multi-Function Timer, 6-bit
ADC, and SYNC Processor.
1.1 Features
1.1.1
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Hardware Features
HC05 Core
Y Low cost, HCMOS technology
40-pin DIP and 42-pin SDIP packages
R 256 Bytes of RAM for HC05BD2
A 384 Bytes of RAM for HC05BD7HC705BD7
5.75K-Bytes of User ROM for HC05BD2
IN 11.75K-Bytes of User ROM for HC05BD7
11.5K-Bytes of User EPROM for HC705BD7
IM 26 Bidirectional I/O lines: 14 dedicated and 12 multiplexed I/O lines. 4 of
the 14 dedicated I/O lines and 6 of the 12 multiplexed I/O lines have max.
+12V or +5V open-drain output buffers
L 16 x 8-bit PWM channels: Two 8-bit PWM channels have +12V open-
E drain outputs: 8 dedicated 8-bit PWM channels have +5V open-drain
output options
R 6-bit ADC with 4 selectable input channels
PMulti-Function Timer (MFT) with Periodic Interrupt
Sync Signal Processor module for processing horizontal, vertical,
composite, and SOG SYNC signals; frequency counting; polarity
detection; polarity controlled HSYNO and VSYNO or extracted VSYNC
outputs, and CLAMP pulse output
DDC12AB† module contains DDC1 hardware and multi-master I2C††
hardware for DDC2AB protocol
Software maskable Edge-Sensitive or Edge and Level-Sensitive External
Interrupt
†DDC is a standard defined by VESA.
††I2C-bus is a proprietary Philips interface bus.
SECTION 1: GENERAL DESCRIPTION
For More Information On This Product,
Go to: www.freescale.com
Page 1
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