
SN54/74LS196 • SN54/74LS197
LOGIC DIAGRAM
13
MR
PL
1
8
CP0
6
CP1
P0
P1
P2
P3
4
10
3
11
J SD Q
KCD Q
J SD Q
KCD Q
J SD Q
KCD Q
J SD Q
KCD Q
5
9
2
12
Q0
Q1
Q2
Q3
LS196
13
MR
PL
1
P0
P1
P2
P3
4
10
3
11
8
CP0
6
CP1
J SD Q
KCD Q
J SD Q
KCD Q
J SD Q
KCD Q
J SD Q
KCD Q
5
9
2
12
Q0
Q1
Q2
Q3
LS197
VCC = PIN 14
GND = PIN 7
= PIN NUMBERS
FAST AND LS TTL DATA
5-2