EN29F002T-55P 데이터 시트보기 (PDF) - Eon Silicon Solution Inc.

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EN29F002T-55P

2 Megabit (256K x 8-bit) Flash Memory

Eon Silicon Solution Inc. 

Revisions List

EN29F002 / EN29F002N

A:

Preliminary

B (2001.07.03):

Table 7. Icc3 is with RESET# pin at full CMOS levels

Pg. 13 Logical Inhibit section now says that if CE , W E , and OE are all logical zero

(not recommended usage), it will be considered a write.

VID is everywhere changed to be VID =11.5 ± 0.5V

C (2001.07.05):

VID is everywhere changed to be VID =11.0 ± 0.5V

“block” changed to “sector” everywhere appropriate.

Deleted Sector Un/Protect flow charts (we have a supplement for that)

RESET# = VID and not VPP on first page.

LACTHUP >= 200mA line removed from first page

Chip erase and Sector Erase command descriptions modified.

DQ7,DQ5,DQ3 status polling descriptions modified.

Table 7 and Table 12 modified

Absolute Maximum Ratings section added

4800 Great America Parkway, Suite 202

32

Santa Clara, CA 95054

Rev. C, Issue Date: 2001/07/05

Tel: 408-235-8680

Fax: 408-235-8685

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