MCP19114T-E/MQ 데이터 시트보기 (PDF) - Microchip Technology

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MCP19114T-E/MQ

Digitally Enhanced Power Analog Synchronous Low-Side PWM Controller

Microchip Technology 

FIGURE 1-1:

MCP19114/5 FLYBACK SYNCHRONOUS QUASI-RESONANT BLOCK DIAGRAM

VIN 4.5V to 42V

IFB

ICOMP

ISP

ISN

IP

DESATN

DESATP

/ ISOUT

VS CHS4

8

OV REF

LIN

OV_REF

CHS2

8

VREF2

LIN

VREF

LIN

VREF2

8

VZC

OV

VREF2

MUX to

GPB1

VIN/n

CHS0

BGAP

VREF

CHS1

RFB_INT

5 kΩ

EN

See Elec Specs

For Clamp Voltages

A1

BG

OC 4 msb

Clamp

VZC

6

VZC

Slope

Comp

Log

A = 10

A2

A2

CHS6

RFB

MUX

EA_SC

CHS5 PWM Comp

IP_C OMP

CHS10

2

LEB

4

ADJ

Offset

Lin

DESAT

MUX

BG AP

VZC

QRS

Bias Gen

LDO1

LDO2

VDD (5V)

AVDD (4V)

VVDD

AVDD

BGAP

CHS3

CHS8

VIN_UVLO

4 msb

CHS9

VIN_OVLO

2 lsb

BGAP

UVLO_REF

+

-

2 lsb

BGAP

OVLO_REF

-

+

UVLO 4V to 20V

Interrupt and Logic to

PWM & PIC

OVLO 8.8V to 44V

PDRV

IP

DESATN

DESATP

VVDD

VVDD

VVDD

4.7 μF

10Ω

PWM Logic

BGAP VDR 2.7V or 5.4V

UVLO

4

5V to 10V VDR

4.7 μF

OV

PWM

Gate

Drive

Timing

4

Gate

Drive

Timing

PGND

VDR

SDRV

ISP

ISN

Place recommended VVDD and VDR 4.7 μF

Capacitors as close to respective pins as possible

PDRV

PGND

GPIO

OV UVLO OVLO VDD_OK

VDD

GPIO

ADC

OSC

PIC CORE

ccd

EN1 EN2

I/O

AGND

PGND MCLR

SDA TEMP DIMI

I/O x 3

BIN (x7 MCP19115)

AGND

PGND

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