74AHC132 데이터 시트보기 (PDF) - NXP Semiconductors.

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74AHC132

Quad 2-input NAND Schmitt trigger

NXP Semiconductors. 

74AHC132; 74AHCT132

Quad 2-input NAND Schmitt trigger

Rev. 06 — 4 May 2009

Product data sheet

1. General description

The 74AHC132; 74AHCT132 is a high-speed Si-gate CMOS device and is pin compatible

with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard

No. 7-A.

The 74AHC132; 74AHCT132 contains four 2-input NAND gates which accept standard

input signals. They are capable of transforming slowly changing input signals into sharply

defined, jitter free output signals. The gate switches at different points for positive-going

and negative-going signals. The difference between the positive voltage VT+ and the

negative VT− is defined as the hysteresis voltage VH.

2. Features

I Balanced propagation delays

I Inputs accept voltages higher than VCC

I Input levels:

N For 74AHC132: CMOS level

N For 74AHCT132: TTL level

I ESD protection:

N HBM EIA/JESD22-A114E exceeds 2000 V

N MM EIA/JESD22-A115-A exceeds 200 V

N CDM EIA/JESD22-C101C exceeds 1000 V

I Multiple package options

I Specified from −40 °C to +85 °C and from −40 °C to +125 °C

3. Ordering information

Table 1. Ordering information

Type number Package

Temperature range Name

Description

74AHC132

74AHC132D

−40 °C to +125 °C SO14

plastic small outline package; 14 leads;

body width 3.9 mm

74AHC132PW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

74AHC132BQ

−40 °C to +125 °C

DHVQFN14 plastic dual in-line compatible thermal enhanced very

thin quad flat package; no leads; 14 terminals;

body 2.5 × 3 × 0.85 mm

Version

SOT108-1

SOT402-1

SOT762-1

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