AD5602/AD5612/AD5622
Data Sheet
Parameter
POWER REQUIREMENTS
VDD
IDD (Normal Mode)
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
POWER EFFICIENCY
IOUT/IDD
A, B, W, Y Versions1
Min
Typ
Max
2.7
5.5
75
100
60
90
0.3
1
0.15
1
96
1 Temperature ranges for A, B versions: −40°C to +125°C, typical at 25°C.
2 Linearity calculated using a reduced code range 64 to 4032.
3 Guaranteed by design and characterization, not production tested.
Unit
V
µA
µA
µA
µA
%
Test Conditions/Comments
DAC active and excluding load current
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
VIH = VDD and VIL = GND
ILOAD = 2 mA, VDD = 5 V
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted.1
Table 3.
Parameter
fSCL3
t1
t2
t3
t4
t5
t6
t7
Test Conditions/Comments2
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
Limit at TMIN, TMAX
Min
Max
100
400
3.4
1.7
4
0.6
60
120
4.7
1.3
160
320
250
100
10
0
3.45
0
0.9
0
70
0
150
4.7
0.6
160
4
0.6
160
4.7
1.3
Unit
KHz
KHz
MHz
MHz
µs
µs
ns
ns
µs
µs
ns
ns
ns
ns
ns
µs
µs
ns
ns
µs
µs
ns
µs
µs
ns
µs
µs
Description
Serial clock frequency
tHIGH, SCL high time
tLOW, SCL low time
tSU;DAT, data setup time
tHD;DAT, data hold time
tSU;STA, setup time for a repeated start condition
tHD;STA, hold time (repeated) start condition
tBUF, bus free time between a stop and a start
condition
Rev. D | Page 4 of 24