AD8106(2016) 데이터 시트보기 (PDF) - Analog Devices
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AD8106 Datasheet PDF : 22 Pages
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Data Sheet
TIMING CHARACTERISTICS
Table 2.
Parameter
t1
t2
t3
t4
t5
t6
–
–
–
Limit at TMIN, TMAX
20
100
20
100
0
50
8
100
200
1
CLK
0
D0 TO D4 1
A0 TO A2
0
t2
t1
t3
1 = LATCHED
UPDATE
0 = TRANSPARENT
AD8106/AD8107
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
Description
Data setup time
CLK pulse width
Data hold time
CLK pulse separation
CLK to UPDATE delay
UPDATE pulse width
Propagation delay, UPDATE to switch on or off
CLK, UPDATE rise and fall times
RESET time
t4
Figure 2. Timing Diagram
t5
t6
Table 3. Logic Levels
VIH
RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE
2.0 V min
VIL
RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE
0.8 V max
IIH
RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE
20 µA max
IIL
RESET, CLK, D0, D1, D2, D3, D4,
A0, A1, A2, CE, UPDATE
−400 µA min
Rev. A | Page 5 of 22
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