AD5425_05 데이터 시트보기 (PDF) - Analog Devices

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AD5425_05

8-Bit, High Bandwidth Multiplying DAC with Serial Interface

Analog Devices 

AD5425

SINGLE-SUPPLY APPLICATIONS

Current Mode Operation

In the current mode circuit of Figure 32, IOUT2 and hence IOUT1

is biased positive by an amount applied to VBIAS. In this

configuration, the output voltage is given by

VOUT = [D × (RFB/RDAC) × (VBIAS − VIN)] + VBIAS

As D varies from 0 to 255, the output voltage varies from

VOUT = VBIAS to VOUT = 2VBIAS − VIN

VDD

VDD

RFB

VIN

VREF

IOUT1

IOUT2

GND

C1

AA11

VOUT

VBIAS

NOTES:

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE

REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 32. Single-Supply Current Mode Operation

VBIAS should be a low impedance source capable of sinking and

sourcing all possible variations in current at the IOUT2 terminal

without any problems.

It is important to note that VIN is limited to low voltages because

the switches in the DAC ladder no longer have the same source-

drain drive voltage. As a result, their on resistance differs and

this degrades the linearity of the DAC.

Voltage Switching Mode of Operation

Figure 33 shows this DAC operating in the voltage switching

mode. The reference voltage VIN is applied to the IOUT1 pin,

IOUT2 is connected to AGND, and the output voltage is available

at the VREF terminal. In this configuration, a positive reference

voltage results in a positive output voltage, making single-

supply operation possible. The output from the DAC is voltage

at a constant impedance (the DAC ladder resistance), thus an

op amp is necessary to buffer the output voltage. The reference

input no longer sees constant input impedance, but one that

varies with code. So, the voltage input should be driven from a

low impedance source.

VDD

R1

R2

RFB

VDD

VIN

IOUT1

IOUT2

VREF

GND

AA11

VOUT

NOTES:

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 33. Single-Supply Voltage Switching Mode Operation

It is important to note that VIN is limited to low voltage because

the switches in the DAC ladder no longer have the same source

drain drive voltage. As a result, their on resistance differs, which

degrades the linearity of the DAC.

VIN must also not go negative by more than 0.3 V, otherwise an

internal diode turns on, exceeding the maximum ratings of the

device. In this type of application, the full range of the DAC

multiplying capability is lost.

POSITIVE OUTPUT VOLTAGE

Note that the output voltage polarity is opposite to the VREF

polarity for dc reference voltages. To achieve a positive voltage

output, an applied negative reference to the input of the DAC is

preferred over the output inversion through an inverting

amplifier because of the resistor tolerance errors. To generate a

negative reference, the reference can be level shifted by an

op amp such that the VOUT and GND pins of the reference

become the virtual ground and −2.5 V respectively, as shown

in Figure 34.

ADR03

VOUT VIN

GND

+5V

VDD = 5V

VDD

–2.5V

VREF

GND

–5V

RFB

IOUT1

IOUT2

C1

VOUT = 0V TO +2.5V

NOTES:

1ADDITIONAL PINS OMITTED FOR CLARITY.

2C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 34. Positive Voltage Output with Minimum of Components

Rev. A | Page 16 of 28

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