XRT79L71IB 데이터 시트보기 (PDF) - Exar Corporation

부품명

상세내역

제조사

XRT79L71IB

1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE

Exar Corporation 

PRELIMINARY

XRT79L71

REV. P2.0.0

1-CHANNEL DS3/E3 CLEAR-CHANNEL FRAMERLIU COMBO - CC/HDLC ARCHITECTURE

FIGURE 70. A SIMPLISTIC ILLUSTRATION OF THE ROLE/FUNCTION OF THE JITTER ATTENUATOR PLL BLOCK WITHIN THE XRT71D03 DEVICE

156

FIGURE 71. A SIMPLE ILLUSTRATION OF THE JITTER TRANSFER CHARACTERISTICS OF EACH JITTER ATTENUATOR PLL (WITHIN THE

XRT79L71) ................................................................................................................................................................. 157

FIGURE 72. ILLUSTRATION OF THE PHYSICAL ARCHITECTURE OF 2-CHANNEL JITTER ATTENUATOR FIFO ARCHITECTURE WITHIN THE JITTER

ATTENUATOR BLOCK .................................................................................................................................................... 158

FIGURE 73. ILLUSTRATION OF THE JITTER ATTENUATOR FIFO AND THE FIFO_WRITE AND FIFO_READ POINTERS. ..................... 160

TABLE 24: THE RELATIONSHIP BETWEEN THE STATES OF BITS 2 AND 0 (WITHIN THE JITTER ATTENUATOR CONTROL REGISTER) AND THE

(1) ENABLE/DISABLE STATE OF THE JITTER ATTENUATOR, AND (2) THE SIZE OF THE JITTER ATTENUATOR FIFO ............. 162

4.2.6.3 THE TRANSMIT CONTROL BLOCK ........................................................................................................................ 165

4.2.6.4 THE TRANSMIT PULSE SHAPING BLOCK .............................................................................................................. 165

FIGURE 74. DS3 PULSE TEMPLATE MEASUREMENT - TAKEN WITH 0 FEET OF CABLE LOSS WITH THE TXLEV BIT SET TO "0"............ 167

FIGURE 75. DS3 PULSE TEMPLATE MEASUREMENT - TAKEN WITH 225 FEET OF CABLE LOSS WITH THE TXLEV BIT-FIELD SET TO "0"168

FIGURE 76. DS3 PULSE TEMPLATE MEASUREMENTS - TAKEN WITH 225 FEET OF CABLE LOSS WITH THE TXLEV BIT-FIELD SET TO "1"169

FIGURE 77. DS3 PULSE TEMPLATE MEASUREMENT - TAKEN WITH 450 FEET OF CABLE LOSS WITH THE TXLEV BIT-FIELD SET TO "1"170

4.2.6.5 THE TRANSMIT LINE DRIVER BLOCK ................................................................................................................... 170

4.2.6.6 THE TRANSMIT DRIVE MONITOR BLOCK .............................................................................................................. 171

FIGURE 78. A SCHEMATIC DESIGN, DEPICTING THE REQUIRED CONNECTIONS FOR EXTERNAL TRANSMIT DRIVE MONITORING.......... 172

FIGURE 79. A SCHEMATIC DESIGN, DEPICTING THE REQUIRED CONNECTIONS FOR INTERNAL TRANSMIT DRIVE MONITORING ........... 175

4.2.6.7 INTERFACING THE TRANSMIT DS3/E3 LIU BLOCK TO THE LINE ........................................................................... 177

FIGURE 80. SCHEMATIC DESIGN, DEPICTING HOW TO INTERFACE THE TRANSMIT DS3/E3 LIU BLOCK (OF THE XRT79L71) TO THE LINE

177

4.3 THE RECEIVE DIRECTION .......................................................................................................................... 178

FIGURE 81. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY WHENEVER THE XRT79L71 HAS

BEEN CONFIGURED TO OPERATE IN THE DS3 CLEAR-CHANNEL FRAMER MODE............................................................... 178

4.3.1 RECEIVE DS3 LIU BLOCK....................................................................................................................................... 178

FIGURE 82. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS

BEEN CONFIGURED TO OPERATE IN THE DS3 CLEAR-CHANNEL FRAMER MODE (WITH THE RECEIVE DS3 LIU BLOCK HIGHLIGHTED)

179

FIGURE 83. ILLUSTRATION OF THE RECEIVE DS3/E3 LIU BLOCK WITHIN THE XRT79L71 .............................................................. 180

4.3.1.1 INTERFACING THE RECEIVE DS3/E3 LIU BLOCK TO THE LINE ............................................................................. 180

FIGURE 84. SCHEMATIC DESIGN, DEPICTING HOW TO INTERFACE THE RECEIVE DS3/E3 LIU BLOCK (OF THE XRT79L71) TO THE LINE181

4.3.1.2 THE AUTOMATIC GAIN CONTROL BLOCK ............................................................................................................. 181

4.3.1.3 THE RECEIVE EQUALIZER BLOCK ........................................................................................................................ 182

4.3.1.4 THE CLOCK AND DATA RECOVERY BLOCK .......................................................................................................... 183

4.3.1.5 THE SFM (SINGLE-FREQUENCY MODE) SYNTHESIZER BLOCK ............................................................................. 186

FIGURE 85. A SIMPLE ILLUSTRATION THAT DEPICTS HOW THE SFM SYNTHESIZER BLOCK FUNCTIONS WHENEVER IT HAS BEEN CONFIGURED

TO OPERATE IN THE SFM MODE ................................................................................................................................... 187

FIGURE 86. A SIMPLE ILLUSTRATION THAT DEPICTS HOW THE SFM SYTHESIZER BLOCK FUNCTIONS WHENEVER IT HAS BEEN CONFIGURED

TO OPERATE IN THE MULTIPLEXER MODE ...................................................................................................................... 189

FIGURE 87. ILLUSTRATION OF RECOMMENDATIONS FOR THE DS3CLK/SFMCLK AND E3CLK INPUT PINS, IF THE SFM SYNTHESIZER BLOCK

IS CONFIGURED TO OPERATE IN THE MULTIPLEXER MODE, ONLY TO SUPPORT DS3 MODE OPERATION. .......................... 191

4.3.1.6 THE LOS DECLARATION AND CLEARANCE CRITERIA FOR DS3 APPLICATIONS ..................................................... 192

4.3.1.7 JITTER ATTENUATOR BLOCK .............................................................................................................................. 196

4.3.1.8 THE B3ZS DECODER BLOCK .............................................................................................................................. 196

4.3.1.9 PERFORMANCE CHARACTERISTICS OF THE RECEIVE DS3 LIU BLOCK ................................................................. 196

FIGURE 88. ILLUSTRATION OF TEST SET-UP TO PERFORM THE RECEIVE SENSITIVITY LOW-LEVEL TEST ......................................... 197

TABLE 25: RECEIVE SENSITIVITY TEST RESULTS (DS3 APPLICATIONS).......................................................................................... 198

FIGURE 89. ILLUSTRATION OF TEST SET-UP USED TO TEST THE XRT79L71 FOR INTERFERENCE MARGIN ...................................... 198

TABLE 26: INTERFERENCE MARGIN TEST RESULTS FOR DS3 APPLICATIONS ................................................................................. 199

4.3.1.10 Receive DS3/E3 LIU Block Interrupts .......................................................................................................... 199

4.3.2 RECEIVE DS3 FRAMER BLOCK ............................................................................................................................. 199

FIGURE 90. ILLUSTRATION OF THE FUNCTIONAL BLOCK DIAGRAM OF THE RECEIVE DIRECTION CIRCUITRY, WHENEVER THE XRT79L71 HAS

BEEN CONFIGURED TO OPERATE IN THE DS3 CLEAR-CHANNEL FRAMER MODE (WITH THE RECEIVE DS3/E3 FRAMER BLOCK HIGH-

LIGHTED) ...................................................................................................................................................................... 200

4.3.2.1 THE FRAME-ACQUISITION MODE ................................................................................................................ 201

FIGURE 91. THE STATE MACHINE DIAGRAM FOR THE RECEIVE DS3 FRAMER BLOCK'S FRAME ACQUISITION/MAINTENANCE ALGORITHM

201

FIGURE 92. THE STATE MACHINE DIAGRAM FOR THE RECEIVE DS3 FRAMER BLOCK'S FRAME ACQUISTION/MAINTENANCE ALGORITHM (WITH

THE F-BIT SEARCH STATE SHADED).............................................................................................................................. 202

FIGURE 93. THE STATE MACHINE DIAGRAM FOR THE RECEIVE DS3 FRAMER BLOCK'S FRAME ACQUISTION/MAINTENANCE ALGORITHM (WITH

THE M-BIT SEARCH STATE SHADED)............................................................................................................................. 204

TABLE 27: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (FRAMING WITH VALID P-BITS) WITHIN THE RX DS3 CONFIGURATION AND

STATUS REGISTER, AND THE RESULTING FRAMING ACQUISITION CRITERIA ..................................................................... 205

4.3.2.2 THE FRAME-MAINTENANCE MODE - THE OOF/LOF DEFECT DECLARATION CRITERIA ..................... 205

TABLE 28: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (F-SYNC ALGO) WITHIN THE RECEIVE DS3 CONFIGURATION AND STATUS

VI

Share Link: