XRT83SL38 데이터 시트보기 (PDF) - Exar Corporation
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XRT83SL38 Datasheet PDF : 89 Pages
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XRT83SL38
OCTAL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.1.0
SIGNAL NAME
TQFP
PIN #
BGA
LEAD #
TYPE
DESCRIPTION
EQC4
194
A6
EQC3
EQC2
EQC1
EQC0
193
B7
192
A7
191
C7
190
D7
RDY_DTACK 194
A6
CS
193
B7
ALE_AS
192
A7
RD_DS
191
C7
WR_R/W
190
D7
I Equalizer Control Input 4 - Hardware mode
This pin together with pins EQC[3:0] is used to control the transmit pulse
shaping, transmit line build-out (LBO) and receive monitoring while operating
at one of either the T1, E1 or J1 clock rates/modes. See “Receive Equalizer
Control and Transmit Line Build-Out Settings” on page 29. for description of
Transmit Equalizer Control bits.
Equalizer Control Input 3
Equalizer Control Input 2
Equalizer Control Input 1
Equalizer Control Input 0
NOTES:
1. In Hardware mode all transmit channels share the same pulse
setting controls function.
2. All channels of an XRT83L38 must operate at the same clock rate,
either the T1, E1 or J1 modes.
O In Host mode, these pins perform various microprocessor functions. See
I “Microprocessor Interface” on page 11.
I NOTE: Internally pulled “Low” with a 50kΩ resistor.
I
I
RXTSEL
83
U11
I Receiver Termination Select
In Hardware mode, when this pin is “Low” the receive line termination is
determined only by an external resistor. When “High”, the receive termination
is realized by the internal resistor or the combination of internal and external
resistors. These conditions are described in the table below.
NOTE: In Hardware mode all channels share the same RXTSEL control
function.
RXTSEL
0
1
RX Termination
External
Internal
In Host mode, the RXTSEL_n bits in the channel control registers determine
if the receiver termination is external or internal. However, the function of RXT-
SEL can be transferred to the Hardware pin by setting the TERCNTL bit (bit
6) to “1” in the register address hex 0x82.
NOTE: This pin is internally pulled “Low” with a 50kΩ resistor.
18
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