S25FL064A0LNFI003 데이터 시트보기 (PDF) - Spansion Inc.

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S25FL064A0LNFI003

64 Megabit CMOS 3.0 Volt Flash Memory with 50MHz SPI (Serial Peripheral Interface) Bus

Spansion Inc. 

Data Sheet (Preliminary)

Figure 9.3 Read Identification (RDID) Command Sequence and Data-Out Sequence

CS#

Mode 3

SCK

Mode 0

SI

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31

Command

Hi-Z

SO

Manufacturer Identification

MSB

Device Identification

15 14 13

32 1 0

Table 9.1 Read Identification (RDID) Data-Out Sequence

Manufacturer Identification

01h

Device Identification

Memory Type

Memory Capacity

02h

16h

9.4

Write Enable (WREN)

The Write Enable (WREN) command (see Figure 9.4) sets the Write Enable Latch (WEL) bit to a 1, which

enables the device to accept a Write Status Register, program, or erase command. The WEL bit must be set

prior to every Page Program (PP), Erase (SE or BE) and Write Status Register (WRSR) command.

The host system must first drive CS# low, write the WREN command, and then drive CS# high.

Figure 9.4 Write Enable (WREN) Command Sequence

CS#

SCK

Mode 3

Mode 0

SI

01 23 4 567

Command

Hi-Z

SO

9.5

Write Disable (WRDI)

The Write Disable (WRDI) command (see Figure 9.5) resets the Write Enable Latch (WEL) bit to a 0, which

disables the device from accepting a Write Status Register, program, or erase command. The host system

must first drive CS# low, write the WRDI command, and then drive CS# high.

Any of following conditions resets the WEL bit:

„ Power-up

„ Write Disable (WRDI) command completion

„ Write Status Register (WRSR) command completion

„ Page Program (PP) command completion

„ Sector Erase (SE) command completion

„ Bulk Erase (BE) command completion

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S25FL064A

S25FL064A_00_C0 September 6, 2006

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