MAX5501(2008) 데이터 시트보기 (PDF) - Maxim Integrated
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MAX5501 Datasheet PDF : 14 Pages
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Low-Power, Quad, 12-Bit
Voltage-Output DACs with Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(MAX5500 (VDD = +5V ±10%, VREFAB = VREFCD = 2.5V), MAX5501 (VDD = +3V ±10%, VREFAB = VREFCD = 1.5V), VAGND = VDGND = 0,
RL = 5kΩ, CL = 100pF, TA = TMIN to TMAX, unless otherwise noted. Typical values at TA = +25°C. Output buffer connected in unity-
gain configuration (Figure 9).)
PARAMETER
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
DYNAMIC PERFORMANCE
Voltage Output Slew Rate
Output Settling Time
Output Voltage Swing
Current into FB_
OUT_ Leakage Current in
Shutdown
Startup Time Exiting Shutdown
Mode
Digital Feedthrough
Digital Crosstalk
POWER SUPPLIES
Supply Voltage
Supply Current
Supply Current in Shutdown
SYMBOL
CONDITIONS
VOH
VOL
ISOURCE = 2mA
ISINK = 2mA
SR
To ±0.5 LSB, VSTEP = 2.5V
MAX5500A/MAX5500B
To ±0.5 LSB, VSTEP = 2.5V
MAX5501A/MAX5501B
Rail-to-rail (Note 2)
RL = ∞
MAX5500A/MAX5500B
MAX5501A/MAX5501B
CS =VDD, fIN = 100kHz
MAX5500A/MAX5500B
VDD
MAX5501A/MAX5501B
IDD
(Note 3)
(Note 3)
MIN
TYP
MAX
UNITS
VDD - 0.5
V
0.13
0.4
V
0.6
12
16
0 to VDD
0
±0.01
15
20
5
5
0.1
±1.0
V/µs
µs
V
µA
µA
µs
nV•s
nV•s
4.5
5.5
V
3.0
3.6
0.85
1.1
mA
10
20
µA
Reference Current in Shutdown
(Note 3)
10
20
µA
TIMING CHARACTERISTICS (Figure 6)
SCLK Clock Period
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Fall to SCLK Rise Setup
Time
tCP
tCH
tCL
tCSS
SCLK Rise to CS Rise Hold
Time
tCSH
DIN Setup Time
tDS
DIN Hold Time
tDH
100
ns
40
ns
40
ns
40
ns
0
ns
40
ns
0
ns
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