MITSUBISHI SEMICONDUCTORS <HVIC>
M81019FP
1200V HIGH VOLTAGE HALF BRIDGE DRIVER
4. FO INPUT TIMING DIAGRAM
When FO is pulled down to low level in case the FO of other phases becomes low level (fault happened) or the MCU/
DSP sets FO to low level, the outputs (HOUT, LOUT) of the driver will be shut down. As soon as FO goes high again,
the output will respond to the following active input signal.
HIN
LIN
FO
HOUT
LOUT
Note1: Delay times between input and output signals are not shown in the figure above.
Note2: The minimum FO pulse width should be more than 500ns (because of FO input filter circuit).
5. LOW SIDE VCC SUPPLY POWER RESET SEQUENCE
When the VCC supply voltage is lower than power reset trip voltage, the power reset gets active and the outputs (HOUT/
LOUT) become “L”. As soon as the VCC supply voltage goes higher than the power reset trip voltage, the outputs will
respond to the following active input signals.
VCC
VPOR voltage
HIN
LIN
HOUT
LOUT
Note1: Delay times between input and output signals are not shown in the figure above.
7
Aug. 2009