M48TMH1TR 데이터 시트보기 (PDF) - STMicroelectronics
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M48TMH1TR Datasheet PDF : 23 Pages
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REGISTER C
MSB
BIT7
IRQF
BIT6
PF
BIT5
AF
BIT4
UF
BIT3
0
BIT2
0
M48T86
BIT1
0
BIT0
0
IRQF. Interrupt Request Flag
The Interrupt Request Flag (IRQF) bit is set to a
one when one or more of the following are true:
PF = PIE = 1
AF = AIE = 1
UF = UIE = 1
(i.e. IRQF = PF*PIE+AF*AIE+UF*UIE)
PF. Periodic Interrupt Flag
The Periodic Interrupt Flag (PF) is a read-only bit
which is set to a one when an edge is detected on
the selected tap of the divider chain. The RS3-RS0
bits establish the periodic rate. PF is set to a one
independent of the state of the PIE bit. The IRQ
signal is active and will set the IRQF bit. The PF bit
is cleared by a RST or a software read of Register
C.
AF. Alarm Flag
A one in the AF (Alarm Interrupt Flag) bit indicates
that the current time has matched the alarm time.
If the AIE bit is also a one, the IRQ pin will go low
and a one will appear in the IRQF bit. A RST or a
read of Register C will clear AF.
UF. Update Ended Interrupt Flag
The Update Ended Interrupt Flag (UF) bit is set af-
ter each update cycle. When the UIE bit is set to a
one, the one in the UF bit causes the IRQF bit to
be a one. This will assert the IRQ pin. UF is
cleared by reading Register C or an RST.
BIT 0 through 3. Unused Bits
Bit 3-Bit 0 are unused. These bits always read
zero and cannot be written.
REGISTER D
MSB
BIT7
VRT
BIT6
0
BIT5
0
BIT4
0
BIT3
0
BIT2
0
BIT1
0
BIT0
0
VRT. Valid Ram And Time
The Valid RAM and Time (VRT) bit is set to the
one state by STMicroelectronics prior to shipment.
This bit is not writable and should always be a one
when read. If a zero is ever present, an exhausted
internal lithium cell is indicated and both the con-
tents of the RTC data and RAM data are question-
able. This bit is unaffected by RST.
BIT 0 through 6. Unused Bits
The remaining bits of Register D are not usable.
They cannot be written and when read, they will al-
ways read zero.
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