HT45FM03B(2009) 데이터 시트보기 (PDF) - Holtek Semiconductor

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HT45FM03B
(Rev.:2009)

Brushless DC Motor Flash Type 8-Bit MCU

Holtek Semiconductor 

HT45FM03B

and continue counting. The interrupt can be disabled by

ensuring that the Timer/Event Counter Interrupt Enable

bit in the Interrupt Control Register 1, INTC1, is reset to

zero.

As the external timer pin is shared with an I/O pin, to en-

sure that the pin is configured to operate as a pulse

width measurement pin, two things have to happen. The

first is to ensure that the Operating Mode Select bits in

the Timer Control Register place the Timer/Event Coun-

ter in the Pulse Width Measurement Mode, the second

is to ensure that the port control register configures the

pin as an input.

Programmable Frequency Divider - PFD

The PFD output is pin-shared with the I/O pin PD0. The

PFD on/off function and its timer source are selected via

configuration option, however, if not selected, the pin

can operate as a normal I/O pin. The timer overflow sig-

nal is the clock source for the PFD circuit. The output

frequency is controlled by loading the required values

into the timer register and if available the timer prescaler

registers to give the required frequency. The timer/event

counter, driven by the system clock and if applicable, di-

vided by the prescaler value, will begin to count-up from

this preloaded register value until full, at which point an

overflow signal will be generated, causing the PFD out-

put to change state. The counter will then be automati-

cally reloaded with the preload register value and once

again continue counting-up.

For the PFD output to function, it is essential that the

corresponding bit of the Port D control register PDC bit 0

is setup as an output. If setup as an input the PFD output

will not function, however, the pin can still be used as a

normal input pin. The PFD output will only be activated if

bit PD0 is set to ²1². This output data bit is used as the

on/off control bit for the PFD output. Note that the PFD

output will be low if the PD0 output data bit is cleared to

²0².

Using this method of frequency generation, and if a

crystal oscillator is used for the system clock, very pre-

cise values of frequency can be generated.

Bits T0PSC0~T0PSC2 of the TMR0C register are used

to define the pre-scaling stages of the internal clock

sources of Timer/Event Counter 0. Bits T1PSC0~

T1PSC2 of the TMR1C register are used to define the

pre-scaling stages of the internal clock sources of

Timer/Event Counter 1. The Timer/Event Counter 0 and

Timer/Event Counter 1 overflow signals can be used to

generate signals for the PFD and Timer Interrupt.

I/O Interfacing

The Timer/Event Counter 0 and Timer/Event Counter 1,

when configured to run in the event counter or pulse

width measurement mode, require the use of the exter-

nal PB7/TMR0/TMR1 pin for correct operation. As this

pin is a shared pin it must be configured correctly to en-

sure it is setup for use as a Timer/Event Counter 0 and

Timer/Event Counter 1 input and not as a normal I/O pin.

This is implemented by ensuring that the mode select

bits in the Timer/Event Counter 0 or Timer/Event Coun-

ter 1 control register, selects either the event counter or

pulse width measurement mode. Additionally the Port

Control Register PBC bit 7 must be set high to ensure

that the pin is setup as an input. Any pull-high resistor

configuration option on this pin will remain valid even if

the pin is used as a Timer/Event Counter 0 or

Timer/Event Counter 1 input.

T im e r O v e r flo w

P F D C lo c k

P D 0 D a ta

P F D O u tp u t a t P D 0

PFD Output Control

Rev. 1.00

28

December 16, 2009

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