HT45FM03B(2009) 데이터 시트보기 (PDF) - Holtek Semiconductor
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HT45FM03B Datasheet PDF : 83 Pages
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HT45FM03B
hand, using instructions to preload data into the high
byte timer register will result in the data being directly
written to the high byte register. At the same time the
data in the low byte buffer will be transferred into its as-
sociated low byte register. For this reason, when
preloading data into the 16-bit timer registers, the low
byte should be written first. It must also be noted that to
read the contents of the low byte register, a read to the
high byte register must first be executed to latch the
contents of the low byte buffer into its associated low
byte register. After this has been done, the low byte reg-
ister can be read in the normal way. Note that reading
the low byte timer register will only result in reading the
previously latched contents of the low byte buffer and
not the actual contents of the low byte timer register.
Timer Control Register - TMR0C, TMR1C
The flexible features of the Holtek microcontroller
Timer/Event Counters enable them to operate in three
different modes, the options of which are determined by
the contents of their respective control register. There
are two timer control registers known as TMR0C and
TMR1C. It is the timer control register together with its
corresponding timer registers that control the full opera-
tion of the Timer/Event Counters. Before the timers can
be used, it is essential that the appropriate timer control
register is fully programmed with the right data to ensure
its correct operation, a process that is normally carried
out during program initialisation.
To choose which of the three modes the timer is to oper-
ate in, either in the timer mode, the event counting mode
or the Pulse Width Measurement mode, bits 7 and 6 of
the Timer Control Register, which are known as the bit
pair T0M1/T0M0 or T1M1/T1M0 respectively, depend-
ing upon which timer is used, must be set to the required
logic levels. The timer-on bit, which is bit 4 of the Timer
Control Register and known as T0ON or T1ON, de-
pending upon which timer is used, provides the basic
on/off control of the respective timer. Setting the bit high
allows the counter to run, clearing the bit stops the coun-
ter. Bits 0~2 of each Timer Control Register determine
the division ratio of the input clock prescaler. The
prescaler bit settings have no effect if an external clock
source is used. If the timer is in the event count or Pulse
Width Measurement mode, the active transition edge
level type is selected by the logic level of bit 3 of the
Timer Control Register which is known as T0E or T1E,
depending upon which timer is used.
Configuring the Timer Mode
In this mode, the Timer/Event Counter can be setup to
measure fixed time intervals, providing an internal inter-
rupt signal each time the Timer/Event Counter over-
flows. To operate in this mode, the Operating Mode
Select bit pair in the Timer Control Register must be set
to the correct value as shown.
Control Register Operating Mode
Select Bits for the Timer Mode
Bit7 Bit6
10
In this mode the internal clock, fSYS, is used as the
Timer/Event Counter clock. However, this clock source
is further divided by a prescaler, the value of which is de-
termined by the Prescaler Rate Select bits, which are
bits 0~2 in the Timer Control Register. After the other
bits in the Timer Control Register have been setup, the
enable bit, which is bit 4 of the Timer Control Register,
can be set high to enable the Timer/Event Counter to
run. Each time an internal clock cycle occurs, the
Timer/Event Counter increments by one. When it is full
and overflows, an interrupt signal is generated and the
Timer/Event Counter will reload the value already
loaded into the preload register and continue counting.
The interrupt can be disabled by ensuring that the
Timer/Event Counter Interrupt Enable bit in the Interrupt
Control Register, INTC1, is reset to zero.
Configuring the Event Counter Mode
In this mode, a number of externally changing logic
events, occurring on the external timer pin, can be re-
corded by the Timer/Event Counter. To operate in this
mode, the Operating Mode Select bit pair in the Timer
Control Register must be set to the correct value as
shown.
Control Register Operating Mode
Select Bits for the Event Counter Mode
Bit7 Bit6
01
P r e s c a le r O u tp u t
In c re m e n t
T im e r C o n tr o lle r
T im e r + 1
T im e r + 2
Timer Mode Timing Chart
T im e r + N
T im e r + N + 1
E x te rn a l E v e n t
In c re m e n t
T im e r C o u n te r
Rev. 1.00
T im e r + 1
T im e r + 2
Event Counter Mode Timing Chart
25
T im e r + 3
December 16, 2009
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