D a ta B u s
W r ite C o n tr o l R e g is te r
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
R e a d D a ta R e g is te r
IN T 0 A fo r P B 4
IN T 0 B fo r P B 5
IN T 0 C fo r P B 6
T M R 0 fo r P B 7
T M R 1 fo r P B 7
T o A /D C o n v e rte r
O P V IN N
O PO UT
P u ll- H ig h
C o n tr o l B it O p tio n
DQ
CK Q
S
V DD
W eak
P u ll- u p
D a ta B it
DQ
CK Q
S
M
U
X
PCR2
PCR1
PCR0
A n a lo g
In p u t
S e le c to r
A C S 2~A C S 0
PB Input/Output Ports
HT45FM03B
P B 0 /A N 0
P B 1 /A N 1
P B 2 /A N 2 /O P O U T
P B 3 /A N 3 /O P V IN N
P B 4 /A N 4 /IN T 0 A
P B 5 /A N 5 /IN T 0 B
P B 6 /A N 6 /IN T 0 C
P B 7 /A N 7 /T M R 0 /T M R 1
V DD
D a ta B u s
P u ll- H ig h
C o n tr o l B it O p tio n
DQ
W eak
P u ll- u p
W r ite C o n tr o l R e g is te r
C h ip R e s e t
CK Q
S
R e a d C o n tr o l R e g is te r
D a ta B it
DQ
W r ite D a ta R e g is te r
P F D o r P W M W a v e fo rm
R e a d D a ta R e g is te r
CK Q
S
M
U
X
M
U
X
P F D /P W M O p tio n
PD0/PFD and PC Input/Output Ports
P D 0 /P F D
P C 0 /P W M 0 H
P C 1 /P W M 0 L
P C 2 /P W M 1 H
P C 3 /P W M 1 L
P C 4 /P W M 2 H
P C 5 /P W M 2 L
Rev. 1.00
21
December 16, 2009