CY7C1486BV25-250BGI 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1486BV25-250BGI

72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined Sync SRAM

Cypress Semiconductor 

CY7C1480BV25

CY7C1482BV25, CY7C1486BV25

Switching Waveforms (continued)

Timing for ZZ mode is shown in Figure 9.[23, 24]

Figure 9. ZZ Mode Timing

CLK

ZZ

I SUPPLY

ALL INPUTS

(except ZZ)

t ZZ

t ZZI

I DDZZ

t ZZREC

t RZZI

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

Notes

23. Device must be deselected when entering ZZ mode. See “Truth Table” on page 10 for all possible signal conditions to deselect the device.

24. DQs are in high-Z when exiting ZZ sleep mode.

Document #: 001-15143 Rev. *D

Page 25 of 31

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