ATF16V8C-7JU(2014) 데이터 시트보기 (PDF) - Atmel Corporation

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ATF16V8C-7JU
(Rev.:2014)

High Performance Electrically-Erasable PLD

Atmel Corporation 

3.6 Power-up Reset

Registers of the ATF16V8C are designed to reset during power-up. At a point delayed slightly from VCC crossing

VRST, all registers will be reset to the low state. As a result, the registered output state will always be high on

power-up.

This feature is critical for state machine initialization; however, due to the asynchronous nature of reset and the

uncertainty of how VCC actually rises in the system, the following conditions are required:

1. The VCC rise must be monotonic, from below 0.7V.

2. After reset occurs, all input and feedback setup times must be met before driving the clock term high.

3. The signals from which the clock is derived must remain stable during tPR.

Figure 3-3. Power-up Reset

Power

VRST

tPR

Registered

Outputs

Clock

tS

tW

Table 3-4. Power-up Reset Parameters

Parameter

tPR

VRST

Description

Power-up Reset Time

Power-up Reset Voltage

Typ

Max

Units

600

1,000

ns

3.8

4.5

V

6

ATF16V8C [DATASHEET]

Atmel-0425I-PLD-ATF16V8C-Datasheet_032014

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