AIF120F300N-L(2006) 데이터 시트보기 (PDF) - Astec Semiconductor => Silicon Link

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AIF120F300N-L
(Rev.:2006)

600W, DC-DC Converter Module

Astec Semiconductor => Silicon Link 

Technical Reference Notes

AIF12W300 DC-DC Series

Basic Operation and Features (continued)

Clock Signals (CLK IN, CLK OUT)

The module’s internal clock is accurate and stable over its full operating range and synchronization is not normally required,

but it can reduce noise in paralleled systems.

Clock signals can be wired in series (the CLK OUT pin of one module to the CLK IN pin of the next etc) in which case all the

modules will be synchronized with the first module in the chain. Alternatively, an external clock signal of 5Vpk-pk at 800KHz

±10% can be connected to the CLK IN pins of all the modules.

If the clock input to any module fails, the module will automatically switch back to its internal clock and will continue to

operate normally. The CLK IN and CLK OUT signals are AC coupled, so any module can clock another module regardless of

polarity.

Current Share (CSHARE)

To ensure that all modules in a parallel system accurately share current, the C SHARE pins on each module should be

connected together.

The voltage on the C SHARE pins represents the average load current per module. Each module compares this average with its

own current and adjusts its output voltage to correct the error. In this way the module maintains accurate current sharing.

Note: The –SENSE and +SENSE pins of each module must also be connected together to ensure accurate current sharing.

MODEL: AIF12W300 SERIES

JUNE 2006

SHEET 17 OF 37

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