AD7918BRUZ(RevE) 데이터 시트보기 (PDF) - Analog Devices

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AD7918BRUZ
(Rev.:RevE)

8-Channel, 1 MSPS, 8-/10-/12-Bit ADCs with Sequencer in 20-Lead TSSOP

Analog Devices 

AD7908/AD7918/AD7928

Data Sheet

Parameter

LOGIC OUTPUTS

Output High Voltage, VOH

Output Low Voltage, VOL

Floating-State Leakage Current

Floating-State Output Capacitance3

Output Coding

CONVERSION RATE

Conversion Time

Track-and-Hold Acquisition Time

Throughput Rate

POWER REQUIREMENTS

AVDD

VDRIVE

IDD4

Normal Mode (Static)

Normal Mode (Operational)

Using Auto Shutdown Mode

Full Shutdown Mode

Power Dissipation4

Normal Mode (Operational)

Auto Shutdown Mode (Static)

Full Shutdown Mode

B Version1

Unit

VDRIVE − 0.2

V min

0.4

V max

±1

μA max

10

pF max

Straight (natural) binary

Twos complement

800

ns max

300

ns max

300

ns max

1

MSPS max

2.7/5.25

2.7/5.25

V min/max

V min/max

600

μA typ

2.7

mA max

2

mA max

960

μA typ

0.5

μA max

0.5

μA max

13.5

mW max

6

mW max

2.5

μW max

1.5

μW max

2.5

μW max

1.5

μW max

1 Temperature ranges as follows: B version: –40°C to +85°C.

2 See Terminology section.

3 Sample tested @ 25°C to ensure compliance.

4 See Power vs. Throughput Rate section.

Test Conditions/Comments

ISOURCE = 200 μA, AVDD = 2.7 V to 5.25 V

ISINK = 200 μA

Coding bit set to 1

Coding bit set to 0

16 SCLK cycles with SCLK at 20 MHz

Sine wave input

Full-scale step input

See Serial Interface section

Digital inputs = 0 V or VDRIVE

AVDD = 2.7 V to 5.25 V, SCLK on or off

AVDD = 4.75 V to 5.25 V, fSCLK = 20 MHz

AVDD = 2.7 V to 3.6 V, fSCLK = 20 MHz

fSAMPLE = 250 kSPS

(Static)

SCLK on or off (20 nA typ)

AVDD = 5 V, fSCLK = 20 MHz

AVDD = 3 V, fSCLK = 20 MHz

AVDD = 5 V

AVDD = 3 V

AVDD = 5 V

AVDD = 3 V

Rev. E | Page 6 of 28

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