Advance Information
MT90863
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
BBPD BBPD BBPD
2
1
0
0
0
0
0
0
0
0
0
0
0
0
Backplane Connection Memory (BCM)
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
LBPD LBPD LBPD LBPD
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
Local Connection Memory Low (LCML)
15
14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Local Connection Memory High (LCMH)
Figure 7 - Block Programming Data in the Connection Memories
A7
(Note 1)
A6
A5
A4
A3
A2
A1
A0
Location
0
0
0
0
0
0
0
0 Control Register, CR
0
0
0
0
0
0
0
1 Device Mode Selection Register, DMS
0
0
0
0
0
0
1
0 Internal Mode Selection Register, IMS
0
0
0
0
0
0
1
1 Frame Alignment Register, FAR
0
0
0
0
0
1
0
0 Input Offset Selection Register 0, DOS0
0
0
0
0
0
1
0
1 Input Offset Selection Register 1, DOS1
0
0
0
0
0
1
1
0 Input Offset Selection Register 2, DOS2
0
0
0
0
0
1
1
1 Input Offset Selection Register 3, DOS3
0
0
0
0
1
0
0
0 Input Offset Selection Register 4, DOS4
0
0
0
0
1
0
0
1 Input Offset Selection Register 5, DOS5
0
0
0
0
1
0
1
0 Frame Output Offset Register, FOR0
0
0
0
0
1
0
1
1 Frame Output Offset Register, FOR1
0
0
0
0
1
1
0
0 Address Buffer Register, ABR
0
0
0
0
1
1
0
1 Data Write Register, DWR
0
0
0
0
1
1
1
0 Data Read Register, DRR
1
0
0
0
0
0
0
0 Ch 0
1
0
0
0
0
0
0
1 Ch 1
1
0
0
.
.
.
.
..
1
0
0
1
1
1
1
0 Ch 30
1
0
0
1
1
1
1
1 Ch 31
(Note 2)
1
0
1
0
0
0
0
0 Ch 32
1
0
1
0
0
0
0
1 Ch 33
.
.
.
.
.
.
.
..
1
1
1
1
1
1
1
0 Ch 126
1
1
1
1
1
1
1
1 Ch 127
(Note 3)
Notes:
1. Bit A7 must be high for access to data and connection memory positions. Bit A7 must be low for access to registers.
2. Channels 0 to 31 are used when serial stream is at 2Mb/s.
3. Channels 0 to 127 are used when serial stream is at 8Mb/s
Table 4 - Address Memory Map
11