MT47H128M8HW-25ELITH 데이터 시트보기 (PDF) - Micron Technology

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MT47H128M8HW-25ELITH

1Gb: x4, x8, x16 DDR2 SDRAM

Micron Technology 

1Gb: x4, x8, x16 DDR2 SDRAM

Reset

Figure 80: RESET Function

T0

CK#

CK

CKE

ODT

Command

DM3

READ

T1

NOP2

T2

READ

T3

NOP2

T4

T5

tDELAY

1

NOP2

tCK Ta0

Tb0

tCL tCL tCKE (MIN)

NOP2

PRE

Address

Col n

A10

Col n

All banks

Bank address

DQS3

DQ3

RTT

Bank a

High-Z

High-Z

Bank b

DO DO DO

High-Z

4

High-Z

High-Z

System

RESET

Indicates a break in

time scale

Unknown

RTT On

T = 400ns (MIN)

tRPA

Start of normal5

initialization

sequence

Transitioning Data

Don’t Care

Notes:

1. VDD, VDDL, VDDQ, VTT, and VREF must be valid at all times.

2. Either NOP or DESELECT command may be applied.

3. DM represents DM for x4/x8 configuration and UDM, LDM for x16 configuration. DQS

represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropri-

ate configuration (x4, x8, x16).

4. In certain cases where a READ cycle is interrupted, CKE going HIGH may result in the

completion of the burst.

5. Initialization timing is shown in Figure 43 (page 87).

PDF: 09005aef8565148a

1GbDDR2.pdf – Rev. AA 07/14 EN

126

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2007 Micron Technology, Inc. All rights reserved.

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