MAX5363 데이터 시트보기 (PDF) - Maxim Integrated
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MAX5363 Datasheet PDF : 12 Pages
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Low-Cost, Low-Power, 6-Bit DACs with 3-Wire
Serial Interface in SOT23
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +3.6V (MAX5363), VDD = +4.5V to +5.5V (MAX5364), VDD = +2.7V to +5.5V (MAX5365), RL = 10kΩ, CL = 50pF, TA =
TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.)
PARAMETER
Digital-Analog Glitch Impulse
Wake-Up Time
POWER REQUIREMENTS
Supply Voltage
Supply Current
DIGITAL INPUTS
Input Low Voltage
Input High Voltage
Input Hysteresis
Input Capacitance
Input Leakage Current
SYMBOL
CONDITIONS
Code 31 to code 32
From software shutdown
MAX5363
VDD
MAX5364
MAX5365
No load, all digital inputs at 0 or VDD,
IDD
code = 63
Shutdown mode
VIL
VIH
VH
CIN
(Note 7)
IIN
MIN TYP MAX UNITS
40
nVs
50
µs
2.7
3.6
4.5
5.5
V
2.7
5.5
150
230
µA
1
0.3 ×
VDD
V
0.7 ×
VDD
V
0.05 ×
VDD
V
10
pF
±1
µA
TIMING CHARACTERISTICS
(Figures 3 and 4, VDD = +2.7V to +3.6V (MAX5363), VDD = +4.5V to +5.5V (MAX5364), VDD = +2.7V to +5.5V (MAX5365), RL =
10kΩ, CL = 50pF, TA = TMIN to TMAX, unless otherwise noted. Typical values are TA = +25°C.) (Note 7)
PARAMETER
SCLK Period
SCLK Pulse Width High
SCLK Pulse Width Low
CS Fall to SCLK Rise Setup
Time
SYMBOL
tCP
tCH
tCL
tCSS
CONDITIONS
MIN TYP MAX UNITS
100
ns
40
ns
40
ns
40
ns
SCLK Rise to CS Rise Hold
Time
tCSH
0
ns
DIN Setup Time
DIN Hold Time
SCLK Rise to CS Fall Delay
CS Rise to SCLK Rise Hold
CS Pulse Width High
tDS
tDH
tCS0
tCS1
tCSW
40
ns
0
ns
10
ns
40
ns
100
ns
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